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I/O Timing

Page 53

June 2013

Altera Corporation

Cyclone V Device Datasheet

I/O Timing

Altera offers two ways to determine I/O timing—the Excel-based I/O Timing and the

Quartus II Timing Analyzer.

Excel-based I/O timing provides pin timing performance for each device density and

speed grade. The data is typically used prior to designing the FPGA to get an estimate

of the timing budget as part of the link timing analysis.

The Quartus II Timing Analyzer provides a more accurate and precise I/O timing

data based on the specifics of the design after you complete place-and-route.

f You can download the Excel-based I/O Timing spreadsheet from the Cyclone V

Devices Documentation webpage.

Programmable IOE Delay

Table 59 lists the Cyclone V IOE programmable delay settings.

Programmable Output Buffer Delay

Table 60 lists the delay chain settings that control the rising and falling edge delays of

the output buffer. The default delay is 0 ps.

You can set the programmable output buffer delay in the Quartus II software by

setting the Output Buffer Delay Control assignment to either positive, negative, or

both edges, with the specific values stated here (in ps) for the Output Buffer Delay

assignment.

Table 59. IOE Programmable Delay for Cyclone V Devices

Parameter

Available

Settings

Minimum

Offset

Fast Model

Slow Model

Unit

Industrial Commercial

–C6

–C7

–C8

–I7

–A7

0.508

0.517

0.971

1.187

1.194

1.179

1.160

1.761

1.793

3.291

4.022

3.961

3.999

3.929

0.510

0.519

1.180

1.187

1.195

1.180

1.160

0.508

0.517

0.970

1.186

1.194

1.179

Table 60. Programmable Output Buffer Delay for Cyclone V Devices (1)—Preliminary

Symbol

Parameter

Typical

Unit

DOUTBUF

Rising and/or falling edge

delay

0 (default)

100

150

Note to Table 60:

(1) Pending data extraction from the Quartus II software.

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