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Page 32

Switching Characteristics

Cyclone V Device Datasheet

June 2013

Altera Corporation

HPS Specifications

This section provides HPS specifications and timing for Cyclone V devices.

For HPS reset, the minimum reset pulse widths for the HPS cold and warm reset

signals (HPS_nRST and HPS_nPOR) are six clock cycles of HPS_CLK1.

The data in Table 33 through Table 45 is preliminary and pending silicon

characterization.

HPS Clock Performance

Table 33 lists the HPS clock performance for Cyclone V devices.

QSPI Timing Characteristics

Table 34 lists the queued serial peripheral interface (QSPI) timing characteristics for

Cyclone V devices.

Figure 4 shows the timing diagram for QSPI timing characteristics.

Table 33. HPS Clock Performance for Cyclone V Devices—Preliminary

Symbol/Description

–C6

–C7, –I7

–C8, –A7

Unit

mpu_base_clk

800

600

MHz

main_base_clk

400

300

MHz

Table 34. QSPI Timing Requirements for Cyclone V Devices—Preliminary

Symbol

Description

Min

Typ

Max

Unit

Fclk

CLK clock frequency

—

108

MHz

Tdutycycle

QSPI_CLK duty cycle

TBD

—

TBD

Tdssfrst

Output delay QSPI_SS valid before first clock edge

—

TBD

Tdsslst

Output delay QSPI_SS valid after last clock edge

—

TBD

Tdio

IO Data output delay

–1

—

Tdinmax

Maximum data input delay from falling edge of

QSPI_CLK to data arrival at SoC

—

Figure 4. QSPI Timing Diagram

QSPI_SS

QSPI_CLK

QSPI_DATA

dinmax

dsslst

dio

dssfrst

Data Out

Data In

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