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Switching Characteristics

Page 31

June 2013

Altera Corporation

Cyclone V Device Datasheet

OCT Calibration Block Specifications

Table 31 lists the OCT calibration block specifications for Cyclone V devices.

Figure 3 shows the timing diagram for the oe and dyn_term_ctrl signals.

Duty Cycle Distortion (DCD) Specifications

Table 32 lists the worst-case DCD for Cyclone V devices. The output DCD cycle only

applies to the I/O buffer. It does not cover the system DCD.

Table 31. OCT Calibration Block Specifications for Cyclone V Devices—Preliminary

Symbol

Description

Min

Typ

Max

Unit

OCTUSRCLK

Clock required by OCT calibration blocks

—

MHz

TOCTCAL

Number of OCTUSRCLK clock cycles required for

RS OCT /RT OCT calibration

—

1000

—

Cycles

TOCTSHIFT

Number of OCTUSRCLK clock cycles required for OCT code

to shift out

—

Cycles

TRS_RT

Time required between the dyn_term_ctrl and oe signal

transitions in a bidirectional I/O buffer to dynamically switch

between RS OCT and RT OCT

—

2.5

—

Figure 3. Timing Diagram for the oe and dyn_term_ctrl Signals

Table 32. Worst-Case DCD on I/O Pins for Cyclone V Devices—Preliminary

Symbol

–C6

–C7, –I7

–C8, –A7

Unit

Min

Max

Min

Max

Min

Max

Output Duty Cycle

dyn_term_ctrl

RS_RT

Tristate

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