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Page 26

Switching Characteristics

Cyclone V Device Datasheet

June 2013

Altera Corporation

DSP Block Specifications

Table 25 lists the Cyclone V DSP block performance specifications.

tDRIFT

Frequency drift after PFDENA is disabled for a duration of

100 µs

—

±10

dKBIT

Bit number of Delta Sigma Modulator (DSM)

—

Bits

kVALUE

Numerator of fraction

TBD (1) 8388608

TBD (1)

—

fRES

Resolution of VCO frequency (fINPFD =100 MHz)

—

5.96

—

Notes to Table 24:

(1) Pending silicon characterization.

(2) This specification is limited in the Quartus II software by the I/O maximum frequency. The maximum I/O frequency is different for each I/O standard.

(3) The VCO frequency reported by the Quartus II software takes into consideration the VCO post-scale counter K value. Therefore, if the counter K has

a value of 2, the frequency reported can be lower than the fVCO specification.

(4) This specification is limited by the lower of the two: I/O fMAX or FOUT of the PLL.

(5) A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source with jitter < 120 ps.

(6) FREF is fIN/N, specification applies when N =1.

(7) Peak-to-peak jitter with a probability level of 10–12 (14 sigma, 99.99999999974404% confidence level). The output jitter specification applies to

the intrinsic jitter of the PLL, when an input jitter of 30 ps is applied. The external memory interface clock output jitter specifications use a different

measurement method and are available in Table 30 on page 1–30.

(8) The cascaded PLL specification is only applicable with the following condition:

a. Upstream PLL: 0.59 MHz

≤ Upstream PLL BW < 1 MHz

b. Downstream PLL: Downstream PLL BW>2MHz

(9) High bandwidth PLL settings are not supported in external feedback mode.

(10) External memory interface clock output jitter specifications use a different measurement method, which is available in Table 30 on page 1–30.

Table 24. PLL Specifications for Cyclone V Devices (1)—Preliminary (Part 3 of 3)

Symbol

Parameter

Min

Typ

Max

Unit

Table 25. DSP Block Performance Specifications for Cyclone V Devices—Preliminary

Mode

Performance

Unit

–C6

–C7, –I7

–C8, –A7

Modes using One DSP Block

Independent9x9 Multiplication

340

300

260

MHz

Independent 18 x 19 Multiplication

287

250

200

MHz

Independent 18 x 18 Multiplication

287

250

200

MHz

Independent 27 x 27 Multiplication

250

200

160

MHz

Independent 18 x 25 Multiplication

310

250

200

MHz

Independent 20 x 24 Multiplication

310

250

200

MHz

Two 18 x 19 Multiplier Adder Mode

310

250

200

MHz

18 x 18 Multiplier Added Summed with 36-bit Input

310

250

200

MHz

Modes using Two DSP Blocks

Complex 18 x 19 multiplication

310

250

200

MHz

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