5CEBA2U19C8N datasheet(27/58 Pages) ALTERA

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Switching Characteristics

Page 27

June 2013

Altera Corporation

Cyclone V Device Datasheet

Memory Block Specifications

Table 26 lists the Cyclone V memory block specifications.

To achieve the maximum memory block performance, use a memory block clock that

comes through global clock routing from an on-chip PLL and set to 50% output duty

cycle. Use the Quartus II software to report timing for the memory block clocking

schemes.

When you use the error detection cyclical redundancy check (CRC) feature, there is no

degradation in fMAX.

Periphery Performance

This section describes periphery performance and the high-speed I/O and external

memory interface.

1 Actual achievable frequency depends on design- and system-specific factors. You

must perform HSPICE/IBIS simulations based on your specific design and system

setup to determine the maximum achievable frequency in your system.

Table 26. Memory Block Performance Specifications for Cyclone V Devices—Preliminary

Memory

Mode

Resources Used

Performance

Unit

ALUTs

Memory

–C6

–C7, –I7

–C8, –A7

MLAB

Single port, all supported widths

420

350

300

MHz

Simple dual-port, all supported

widths

420

350

300

MHz

Simple dual-port with read and

write at the same address

340

290

240

MHz

ROM, all supported width

420

350

300

MHz

M10K

Block

Single-port, all supported widths

315

275

240

MHz

Simple dual-port, all supported

widths

315

275

240

MHz

Simple dual-port with the

read-during-write option set to

Old Data, all supported widths

275

240

180

MHz

True dual port, all supported

widths

315

275

240

MHz

ROM, all supported widths

315

275

240

MHz

Min Pulse Width (clock high time)

—

1,450

1,550

1,650

Min Pulse Width (clock low time)

—

1,000

1,200

1,350

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