 |
Datenblatt-Suchmaschine für elektronische Bauteile |
|
|
Datenblatt-Suchmaschine für elektronische Bauteile |
|
5CEBA2U19C8N Datenblatt(PDF) 24 Page - Altera Corporation |
|
|
|||||||||||||||||||||||||||||
5CEBA2U19C8N Datenblatt(HTML) 24 Page - Altera Corporation |
|
|
24 / 58 page  Page 24 Switching Characteristics Cyclone V Device Datasheet June 2013 Altera Corporation Core Performance Specifications This section describes the clock tree, phase-locked loop (PLL), digital signal processing (DSP), and memory block specifications. Clock Tree Specifications Table 23 lists the clock tree specifications for Cyclone V devices. PLL Specifications Table 24 lists the Cyclone V PLL specifications when operating in the commercial (0° to 85°C), industrial (–40° to 100°C), and automotive (–40° to 125°C) junction temperature ranges. Table 23. Clock Tree Performance for Cyclone V Devices—Preliminary Parameter Performance Unit –C6 –C7, –I7 –C8, –A7 Global clock and Regional clock 550 550 460 MHz Peripheral clock 155 155 155 MHz Table 24. PLL Specifications for Cyclone V Devices (1)—Preliminary (Part 1 of 3) Symbol Parameter Min Typ Max Unit fIN Input clock frequency –C6 speed grade 5 — 670 (2) MHz –C7, –I7 speed grades 5 — 622 (2) MHz –C8, –A7 speed grades 5 — 500 (2) MHz fINPFD Integer input clock frequency to the PFD 5 — 325 MHz fFINPFD Fractional input clock frequency to the PFD 50 — TBD (1) MHz fVCO (3) PLL VCO operating range –C6 speed grade 600 — 1600 MHz –C7, –I7 speed grades 600 — 1400 MHz –C8, –A7 speed grades 600 — 1300 MHz tEINDUTY Input clock or external feedback clock input duty cycle 40 — 60 % fOUT Output frequency for internal global or regional clock –C6 speed grade — — 550 (4) MHz –C7, –I7 speed grades — — 550 (4) MHz –C8, –A7 speed grades — — 460 (4) MHz fOUT_EXT Output frequency for external clock output –C6 speed grade — — 667 (4) MHz –C7, –I7 speed grades — — 667 (4) MHz –C8, –A7 speed grades — — 533 (4) MHz tOUTDUTY Duty cycle for external clock output (when set to 50%) 45 50 55 % tFCOMP External feedback clock compensation time — — 10 ns tDYCONFIGCLK Dynamic configuration clock — — 100 MHz tLOCK Time required to lock from end-of-device configuration or deassertion of areset —— 1 ms tDLOCK Time required to lock dynamically (after switchover or reconfiguring any non-post-scale counters/delays) —— 1 ms |
|
Link URL |
| War ALLDATASHEET hilfreich? [ DONATE ] |
Über Alldatasheet | Werbung | Kontakt | Privatsphäre und Datenschutz | Link zum Datenblatt | Linktausch | Hersteller All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
German ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
