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5CEBA2U19C8N Datenblatt(PDF) 15 Page - Altera Corporation |
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5CEBA2U19C8N Datenblatt(HTML) 15 Page - Altera Corporation |
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15 / 58 page ![]() Switching Characteristics Page 15 June 2013 Altera Corporation Cyclone V Device Datasheet Switching Characteristics This section provides performance characteristics of Cyclone V core and periphery blocks for commercial grade devices. Transceiver Performance Specifications This section describes transceiver performance specifications. Table 20 lists the Cyclone V GX, GT, SX, and ST transceiver specifications. Table 20. Transceiver Specifications for Cyclone V GX, GT, SX, and ST Devices—Preliminary (Part 1 of 4) Symbol/ Description Conditions Transceiver Speed Grade 5 (1) Transceiver Speed Grade 6 Transceiver Speed Grade 7 Unit Min Typ Max Min Typ Max Min Typ Max Reference Clock Supported I/O Standards 1.2 V PCML, 1.5 V PCML, 2.5 V PCML, Differential LVPECL (2), HCSL, and LVDS Input frequency from REFCLK input pins (3) — 27 — 550 27 — 550 27 — 550 MHz Rise time 20% to 80% of rising clock edge — — 250 — — 250 — — 250 ps Fall time 80% to 20% of falling clock edge — — 250 — — 250 — — 250 ps Duty cycle — 45 — 55 45 — 55 45 — 55 % Peak-to-peak differential input voltage — 200 — 2000 200 — 2000 200 — 2000 mV Spread-spectrum modulating clock frequency PCIe 30 — 33 30 — 33 30 — 33 kHz Spread-spectrum downspread PCIe — 0to –0.5% —— 0to –0.5% —— 0to –0.5% —— On-chip termination resistors — — 100 — — 100 — — 100 — Ω VICM (AC coupled) — VCCE_GXBL supply (5), (6) VCCE_GXBL supply VCCE_GXBL supply V VICM (DC coupled) HCSL I/O standard for the PCIe reference clock 250 — 550 250 — 550 250 — 550 mV Transmitter REFCLK Phase Noise (4) 10 Hz — — –50 — — –50 — — –50 dBc/Hz 100 Hz — — –80 — — –80 — — –80 dBc/Hz 1 KHz — — –110 — — –110 — — –110 dBc/Hz 10 KHz — — –120 — — –120 — — –120 dBc/Hz 100 KHz — — –120 — — –120 — — –120 dBc/Hz ≥1 MHz — — –130 — — –130 — — –130 dBc/Hz |
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