Member Code

Resource

C6

C5

C4

C2

2

(7)

2

(7)

2

2

PCIe Hard IP Block

1

1

1

1

FPGA Hard Memory Controller

1

1

1

1

HPS Hard Memory Controller

Dual-core

Dual-core

Dual-core

Dual-core

ARM Cortex-A9 MPCore Processor

Related Information

I/O Features in Cyclone V Devices

Provides the number of LVDS channels in each device package.

Package Plan

Table 13: Package Plan for Cyclone V SX Devices

The HPS I/O counts are the number of I/Os in the HPS and does not correlate with the number of HPS-specific I/O

pins in the FPGA. Each HPS-specific pin in the FPGA may be mapped to several HPS I/Os.

F896

(31 mm)

U672

(23 mm)

Member Code

XCVR

HPS I/O

FPGA GPIO

XCVR

HPS I/O

FPGA GPIO

—

—

—

6

181

145

C2

—

—

—

6

181

145

C4

9

181

288

6

181

145

C5

9

181

288

6

181

145

C6

Cyclone V ST

This section provides the available options, maximum resource counts, and package plan for the Cyclone V ST

devices.

The information in this section is correct at the time of publication. For the latest information and to get

more details, refer to the Altera Product Selector.

Related Information

Altera Product Selector

Provides the latest information about Altera products.

Available Options

The following figure shows sample ordering code and lists the options available for Cyclone V ST devices.

Cyclone V Device Overview

Altera Corporation

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CV-51001

Package Plan

14

2013.12.26