PLL Features

The PLLs in the Cyclone V devices support the following features:

• Frequency synthesis

• On-chip clock deskew

• Jitter attenuation

• Programmable output clock duty cycles

• PLL cascading

• Reference clock switchover

• Programmable bandwidth

• User-mode reconfiguration of PLLs

• Low power mode for each fractional PLL

• Dynamic phase shift

• Direct, source synchronous, zero delay buffer, external feedback, and LVDS compensation modes

Fractional PLL

In addition to integer PLLs, the Cyclone V devices use a fractional PLL architecture. The devices have up to

eight PLLs, each with nine output counters. You can use the output counters to reduce PLL usage in two

ways:

• Reduce the number of oscillators that are required on your board by using fractional PLLs

• Reduce the number of clock pins that are used in the device by synthesizing multiple clock frequencies

from a single reference clock source

If you use the fractional PLL mode, you can use the PLLs for precision fractional-N frequency

synthesis—removing the need for off-chip reference clock sources in your design.

The transceiver fractional PLLs that are not used by the transceiver I/Os can be used as general purpose

fractional PLLs by the FPGA fabric.

FPGA General Purpose I/O

Cyclone V devices offer highly configurable GPIOs. The following list describes the features of the GPIOs:

• Programmable bus hold and weak pull-up

emphasis

impedance variation

• On-chip dynamic termination that has the ability to swap between series and parallel termination,

depending on whether there is read or write on a common bus for signal integrity

• Easy timing closure support using the hard read FIFO in the input register path, and delay-locked loop

(DLL) delay chain with fine and coarse architecture

PCIe Gen1 and Gen2 Hard IP

Cyclone V GX, GT, SX, and ST devices contain PCIe hard IP that is designed for performance and ease-of-use.

The PCIe hard IP consists of the MAC, data link, and transaction layers.

Cyclone V Device Overview

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FPGA General Purpose I/O

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2013.12.26