Related Information

Cyclone V Device Family Pin Connection Guidelines

Provides detailed information about power supply pin connection guidelines and power regulator sharing.

Hardware and Software Development

For hardware development, you can configure the HPS and connect your soft logic in the FPGA fabric to

the HPS interfaces using the Qsys system integration tool in the Quartus II software.

For software development, the ARM-based SoC devices inherit the rich software development ecosystem

available for the ARM Cortex-A9 MPCore processor. The software development process for Altera SoCs

follows the same steps as those for other SoC devices from other manufacturers. Support for Linux, VxWorks

and other operating systems is available for the SoCs. For more information on the operating systems support

availability, contact the Altera sales team.

You can begin device-specific firmware and software development on the Altera SoC Virtual Target. The

Virtual Target is a fast PC-based functional simulation of a target development system—a model of a complete

development board that runs on a PC. The Virtual Target enables the development of device-specific

production software that can run unmodified on actual hardware.

Related Information

Altera Worldwide Sales Support

Dynamic and Partial Reconfiguration

The Cyclone V devices support dynamic reconfiguration and partial reconfiguration

Dynamic Reconfiguration

The dynamic reconfiguration feature allows you to dynamically change the transceiver data rates, PMA

settings, or protocols of a channel, without affecting data transfer on adjacent channels. This feature is ideal

for applications that require on-the-fly multiprotocol or multirate support. You can reconfigure the PMA

and PCS blocks with dynamic reconfiguration.

Partial Reconfiguration

Partial reconfiguration is an advanced feature of the device family. If you are interested in using

partial reconfiguration, contact Altera for support.

Note:

Partial reconfiguration allows you to reconfigure part of the device while other sections of the device remain

operational. This capability is important in systems with critical uptime requirements because it allows you

to make updates or adjust functionality without disrupting services.

Apart from lowering cost and power consumption, partial reconfiguration increases the effective logic density

of the device because placing device functions that do not operate simultaneously is not necessary. Instead,

you can store these functions in external memory and load them whenever the functions are required. This

reconfiguration, contact Altera for support.

Cyclone V Device Overview

Altera Corporation

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2013.12.26