Receiver Data Path Feature

Transmitter Data Path Feature

Data Rates(Gbps)

PCS Support

• Custom PHY IP core with

preset feature

• SRIO version 2.1-compliant

x2 and x4 deskew state

machine

• Custom PHY IP core with

preset feature

• SRIO version 2.1-compliant x2

and x4 channel bonding

1.25 to 3.125

SRIO 1.3 and 2.1

Custom PHY IP core with

preset feature

Custom PHY IP core with preset

feature

0.27

and 2.97

SDI, SD/HD, and 3G-

SDI

0.3125

3.125

JESD204A

• Custom PHY IP core with

preset feature

• Signal detect

• Wider spread of

asynchronous SSC

• Custom PHY IP core with

preset feature

• Electrical idle

1.5 and 3.0

Serial ATA Gen1 and

Gen2

• Dedicated deterministic

latency PHY IP core

• Receiver (RX) deterministic

latency state machine

• Dedicated deterministic latency

PHY IP core

• Transmitter (TX) manual

bit-slip mode

0.6144 to 6.144

CPRI 4.1

(14)

0.768 to

3.072

OBSAI RP3

• Custom PHY IP core

• Wider spread of

asynchronous SSC

Custom PHY IP core

Up to 3.75

V-by-One HS

1.62 and 2.7

DisplayPort 1.2

(15)

SoC with HPS

Each SoC combines an FPGA fabric and an HPS in a single device. This combination delivers the flexibility

of programmable logic with the power and cost savings of hard IP in these ways:

• Reduces board space, system power, and bill of materials cost by eliminating a discrete embedded processor

• Allows you to differentiate the end product in both hardware and software, and to support virtually any

interface standard

• Extends the product life and revenue through in-field hardware and software updates

fabric.

FPGA fabric.

Altera Corporation

Cyclone V Device Overview

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SoC with HPS

CV-51001

2013.12.26