Figure 8: ALM for Cyclone V Devices

FPGA Device

1

2

3

4

5

6

7

8

Adaptive

LUT

Full

Adder

Reg

Reg

Full

Adder

Reg

Reg

You can configure up to 25% of the ALMs in the Cyclone V devices as distributed memory using MLABs.

Related Information

Embedded Memory Capacity in Cyclone V Devices on page 20

Lists the embedded memory capacity for each device.

Variable-Precision DSP Block

Cyclone V devices feature a variable-precision DSP block that supports these features:

• Configurable to support signal processing precisions ranging from 9 x 9, 18 x 18 and 27 x 27 bits natively

• A 64-bit accumulator

• A hard preadder that is available in both 18- and 27-bit modes

• Cascaded output adders for efficient systolic finite impulse response (FIR) filters

• Internal coefficient register banks, 8 deep, for each multiplier in 18- or 27-bit mode

• Fully independent multiplier operation

• A second accumulator feedback register to accommodate complex multiply-accumulate functions

• Efficient support for single-precision floating point arithmetic

• The inferability of all modes by the Quartus II design software

Table 16: Variable-Precision DSP Block Configurations for Cyclone V Devices

DSP Block Resource

Multiplier Size (Bit)

Usage Example

1

Three 9 x 9

Low precision fixed point for video

applications

1

Two 18 x 18

Medium precision fixed point in FIR

filters

1

Two 18 x 18 with

accumulate

FIR filters and general DSP usage

Cyclone V Device Overview

Altera Corporation

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CV-51001

Variable-Precision DSP Block

18

2013.12.26