5CSXFC6D datasheet(33/35 Pages) ALTERA

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Changes

Version

Date

• Updated the DDR3 SDRAM for the maximum frequency's soft controller

and the minimum frequency from 300 to 303 for voltage 1.35V.

• Added links to Altera's External Memory Spec Estimator tool to the

topics listing the external memory interface performance.

• Corrected XAUI is supported through the soft PCS in the PCS features

for Cyclone V.

• Added decompression support for the CvP configuration mode.

• Added link to the known document issues in the Knowledge Base.

• Moved all links to the Related Information section of respective topics

for easy reference.

• Corrected the title to the PCIe hard IP topic. Cyclone V devices support

only PCIe Gen1 and Gen2.

• Updated Supporting Feature in Table 1 of Increased bandwidth capacity

to '6.144 Gbps'.

2013.05.06

May 2013

• Updated Description in Table 2 of Low-power high-speed serial interface

to '6.144 Gbps'.

• Updated Description in Table 3 of Cyclone V GT to '6.144 Gbps'.

• Updated the M386 package to M383 for Figure 1, Figure 2 and Figure

• Updated Figure 2 and Figure 3 for Transceiver Count by adding 'F : 4'.

• Updated LVDS in the Maximum Resource Counts tables to include

Transmitter and Receiver values.

• Updated the package plan with M383 for the Cyclone V E device.

• Removed the M301 and M383 packages from the Cyclone V GX C4

device.

• Updated the GPIO count to '129' for the M301 package of the Cyclone V

GX C5 device.

• Updated 5 Gbps to '6.144 Gbps' forCyclone V GT device.

• Updated HPS I/O for U484 (19 mm) in Table 11 with '151' for A2, A4,

A5 and A6.

• Updated Memory (Kb) for Maximum Resource Counts for Cyclone V

SE A4 and A6, SX C4 and C6, ST D6 devices.

• Updated FPGA PLL for Maximum Resource Counts for Cyclone V SE

A2, SX C2, devices.

• Removed '36 x 36' from the Variable-Precision DSP Block.

• Updated Variable-precision DSP Blocks and 18 x 18 Multiplier for

Maximum Resource Counts for Cyclone V SX C4 device.

• Updated the HPS I/O counts for Cyclone V SE, SX, and ST devices.

• Updated Figure 7 which shows the I/O vertical migration table.

• Updated Table 17 for Cyclone V SX C4 device.

• Updated Embedded Memory Capacity and Distribution table for

Cyclone V SE A4 and A6, SX C4 and C6, ST D6 devices.

• Removed 'Counter reconfiguration' from the PLL Features.

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Cyclone V Device Overview

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Document Revision History

CV-51001

2013.12.26

5CSXFC6D Datenblatt(PDF) 33 Page - Altera Corporation

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