5CSXFC6D datasheet(34/35 Pages) ALTERA

34 / 35 page

Changes

Version

Date

• Updated Low-Power Serial Transceivers by replacing 5 Gbps with

6.144 Gbps.

• Removed 'Distributed Memory' symbol.

• Updated the Capability in Table 22 of Backplane support to '6.144 Gbps'.

• Updated Capability in Table 22 of Ring oscillator transmit PLLs with

6.144 Gbps.

• Updated the PCS Support in Table 23 from 5 Gbps to '6 Gbps'.

• Updated the Data Rates (Gbps) in Table 23 of 3 Gbps and 6 Gbps Basic

to '6.144 Gbps'.

• Updated the Data Rates (Gbps) in Table 23 of CPRI 4.1 to '6.144 Gbps'.

• Clarified that partial reconfiguration is an advanced feature. Contact

Altera for support of the feature.

• Updated the pin counts for the MBGA packages.

• Updated the GPIO and transceiver counts for the MBGA packages.

• Updated the GPIO counts for the U484 package of the Cyclone V E A9,

GX C9, and GT D9 devices.

• Updated the vertical migration table for vertical migration of the U484

packages.

• Updated the MLAB supported programmable widths at 32 bits depth.

2012.12.28

December 2012

• Added new MBGA packages and additional U484 packages for

Cyclone V E, GX, and GT.

• Added ordering code for five-transceiver devices for Cyclone V GT and

ST.

• Updated the vertical migration table to add MBGA packages.

• Added performance information for HPS memory controller.

• Removed DDR3U support.

• Updated Cyclone V ST speed grade information.

• Added information on maximum transceiver channel usage restrictions

for PCI Gen2 and CPRI at 4.9152 Gbps transmit jitter compliance.

• Added note on the differences between GPIO reported in Overview

with User I/O numbers shown in the Quartus II software.

• Updated template.

2012.11.19

November 2012

Added support for PCIe Gen2 x4 lane configuration (PCIe-compatible)

2.1

July 2012

Cyclone V Device Overview

Altera Corporation

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Document Revision History

2013.12.26

5CSXFC6D Datenblatt(PDF) 34 Page - Altera Corporation

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