ICS1531 datasheet(24/76 Pages) ICST

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ICS1531 Rev N 12/1/99

December, 1999

Chapter 6

ICS1531 Data Sheet - Preliminary

6.4

Table 6-2 outlines the ICS1531 Register Set.

Note:

For the reserved bits, see Section 6.1, “Reserved Bits”.

For abbreviations and acronyms, see Section 6.3, “Register Set Abbreviations and Acronyms”.

Table 6-2.

Index

Access

Bit #

Bit Name

Brief Description

Reset

Value

00h

Input Control

R/W

7-6 HSYNC_Sel

Select a Schmitt trigger

In_Sel

Select input

Fdbk Div Load

Select load for Feedback Divider

Fdbk_Pol

Select polarity of feedback to Phase/Frequency

Detector

Ref_Pol

Select polarity of external reference

PD_Pol

Select polarity of PDEN to Phase/Frequency Detector

PD_En

Enable Phase/Frequency Detector

01h

Loop Control

R/W. D-PLL.

7-6 Reserved

Reserved

5-4 PSD

Select value for Post-Scaler Divider

Reserved

2-0 PFD

Select Phase/Frequency Detector gain

02h

Fdbk Div 0

R/W. D-PLL.

7-0 FDBK [7-0]

Select value for Feedback Divider LSBs bits 7-0

03h

Fdbk Div 1

R/W. D-PLL.

7-4 Reserved

Reserved

–

3-0 FDBK [11-8]

Select value for Feedback Divider MSBs bits 11-8

04h

DPA Offset

R/W

7-6 Reserved

Reserved

5-0 DPA_OS

Select offset for Dynamic Phase Adjust

05h

DPA Control

R/W. D-DPA.

7-2 Reserved

Reserved

–

1-0 DPA_Res

Select resolution for Dynamic Phase Adjust

06h

Output Enables R/W

Reserved

OE_Tck

Enable clock output to ADC

OE_ADCRCLK

Enable clock output from ADC

OE_ADCSYNC

Enable output for delayed ADCSYNC

FUNC_Sel

Select signal source for ADC_FUNC signal

FUNC_Delay

Select delay for ADC_FUNC signal

1-0 Reserved

Reserved

07h

OSC Divider

R/W

7-0 OSC_Div

Specify value for oscillator divider

08h

Internal Filter

R/W

Shunt_Sel

Select internal filter shunt capacitor size

6-4 Res_Sel

Select internal filter resistor size

3-1 Cap_Sel

Select internal filter capacitor size

Fil_Sel

Select type of loop filter

09h

Reserved

N/A

0Ah

Pixel PLL

Reset/

DPA Reset

Write

7-4 Pixel PLL Reset

Writing 5xh resets pixel PLL and loads working Regs

1h through 3h

N/A

3-0 DPA Reset

Writing xAh resets DPA and loads working Reg 5h

N/A

0Bh-0Fh Reserved

N/A

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