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Chapter 6

ICS1531 Rev N 12/1/99

December, 1999

ICS1531 Data Sheet - Preliminary

6.5.40.4

The CAL_1 Register is used to select (1) delays to calibrate the ADC data delay and (2) the clock delay for

the green and red channels.

6.5.40.5

The CAL_2 Register is used to select (1) delays to calibrate the ADC data delay and (2) the clock delay for

blue channel.

Table 6-42.

CAL1 Register

Bit

Bit Name

Bit Definition

Ac-

cess

Spec.

Func.

Re-

set

3B:7

Reserved

Reserved.

• See Section 6.1, “Reserved Bits”.

• This bit can be programmed to ‘0’.

––

3B:6

ADC_DD [0]

Analog-to-Digital Converter Data (Global) Delay [0].

• This bit works with Regs 3C:4 and 3C:3 for a global delay

of all RGB data output from the ADC.

• This bit is the least-significant bit.

See Reg

37:3

–0

3B:5-

3B:3

G_CD

Green (Channel) Clock Delay.

These bits select a delay (that is, an offset) for use in

calibrating the clock for the green channel. (An acknowledge

of these bits occurs only when the Calibration Regs are

enabled.) When these bits are:

• 0, the clock delay calibration offset is 0.

• 1 or above, the clock delay calibration offset increases.

R/W

See Reg

37:3

–5

3B:2

3B:0

R_CD

Red (Channel) Clock Delay.

These bits select a delay (that is, an offset) for use in

calibrating the clock for the red channel. (An acknowledge of

these bits occurs only when the Calibration Regs are

enabled.) When these bits are:

• 0, the clock delay calibration offset is 0.

• 1 or above, the clock delay calibration offset increases.

R/W

See Reg

37:3

–5

Table 6-43.

CAL2 Register

Bit

Bit Name

Bit Definition

Ac-

cess

Spec.

Func.

Re-

set

3C:7-

3C:5

Bandgap_CAL

Bandgap Calibration.

To calibrate the ICS1531 bandgap voltage, these bits adjust

the current to VRTR, VRTG, and VRTB. (An acknowledge

occurs only when the Test mode is enabled.)

R/W

–

3C:4-

3C:3

ADC_DD [2-1]

Analog-to-Digital Converter Data (Global) Delay [2-1].

• These bits work with Reg 3B:6 for a global delay of all

RGB data output from the ADC.

• These bits are the most-significant bits.

See Reg

37:3

–0

3C:2-

3C:0

B_CD

Blue (Channel) Clock Delay.

These bits select a delay (that is, an offset) for use in

calibrating the clock for the blue channel. (An acknowledge

of these bits occurs only when the Calibration Regs are

enabled.) When these bits are:

• 0, the clock delay calibration offset is 0.

• 1 or above, the clock delay calibration offset increases.

R/W

See Reg

37:3

–5

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