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Chapter 6

ICS1531 Rev N 12/1/99

December, 1999

ICS1531 Data Sheet - Preliminary

6.5.2

The Loop Control Register is used to control the pixel PLL.

00:0

PD_En

Phase/(Frequency) Detector Enable.

This bit is used to enable the Phase/Frequency Detector.

Typically, the signal for this bit is from the source of the VSYNC

signal to a display.

• 0 = The Phase/Frequency Detector is disabled temporarily

and ‘coasts’ (that is, it continues to be disabled) as long as

the signal from the PDEN pin is in an active state. (See

Reg 00:1).

• 1 = The Phase/Frequency Detector is enabled regardless

of the PDEN pin state. (This state overrides Reg 00:1.)

R/W

–

Table 6-4.

Loop Control Register

Bit

Bit Name

Bit Definition

Ac-

cess

Spec.

Func.

Re-

set

01:7-

01:6

Reserved

Reserved.

• See Section 6.1, “Reserved Bits”.

• These bits can be programmed to ‘0’.

––

01:5-

01:4

PSD [1-0]

Post-Scaler Divider [1-0].

• These bits select the division value for the Post-Scaler

Divider (PSD).

• By dividing the frequency output from the voltage-controlled

oscillator (VCO), the PSD can set the ratio of the VCO

frequency output to the pixel clock frequency as follows.

– 0 = Division is by 2, so the ratio is 2:1.

– 1 = Division is by 4, so the ratio is 4:1.

– 2 = Division is by 8, so the ratio is 8:1.

– 3 = Division is by 16, so the ratio is 16:1.

R/W

D-PLL

01:3

Reserved

Reserved.

• See Section 6.1, “Reserved Bits”.

• This bit can be programmed to ‘0’.

––

01:2-

01:0

PFD [2-0]

Phase/Frequency Detector (Gain) [2-0].

These bits select the gain (that is,

µA/2πrad) for the

Phase/Frequency Detector.

• 0 = PFD gain selected is 1 µA.

• 1 = PFD gain selected is 2 µA.

• 2 = PFD gain selected is 4 µA.

• 3 = PFD gain selected is 8 µA.

• 4 = PFD gain selected is 16 µA.

• 5 = PFD gain selected is 32 µA.

• 6 = PFD gain selected is 64 µA.

• 7 = PFD gain selected is 128 µA.

R/W

D-PLL

Table 6-3.

Input Control Register (Continued)

Bit

Bit Name

Bit Definition

Ac-

cess

Spec.

Func.

Re-

set

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