ICS1531 datasheet(68/76 Pages) ICST

68 / 76 page

ICS1531 Rev N 12/1/99

December, 1999

Chapter 10

Timing Diagrams

ICS1531 Data Sheet - Preliminary

10.3.2

Two-Pixels-per-Clock Mode Timing

For 2-pixels-per-clock mode, Reg 30:6 must be cleared to ‘0’. Table 10-4 lists pixel characteristics for this

mode, as determined by Reg 2:0. (Both ‘A’ and ‘B’ channel pixels are pipelined and aligned with the rising

edge of the ADCRCLK.) Table 10-5 lists time measures for this mode, and Figure 10-6 shows timing

characteristics.

Figure 10-6.

AC Timing for 2-Pixels-per-Clock Mode

Table 10-4.

Pixel Characteristics for 2-Pixels-per-Clock Mode

Reg 2:0

Setting

Pixel Characteristics When Reg 30:6 is Cleared to ‘0’

Total Number of Pixels

Pixel Output

What the Pixels Represent

Total number is even.

Output is on Channel ‘A’. Samples taken on half-rate ADCRCLK’s rising edge.

Total number is odd.

Output is on Channel ‘B’. Samples taken on half-rate ADCRCLK’s falling edge.

Table 10-5.

Timing for 2-Pixels-per-Clock Mode

Time

Period

Timing Description

Min

Typ

Max

Units

Tp, Td

CLK Period, CLK Duty Cycle

–

See Table 10-3.–

CLK Rise Time to ADCRCLK Rise Time

–

2.6

–

ACDRCLK Period

–

t2 = 2

× Tp

–

ACDRCLK Fall Time to ADCSYNC Rise Time

–

TBD

–ns

Digital Data Transition

3.8

TBD

P-4

P-2

P-3

P-5

P-1

P+1

P+2

P-6

P+3

P+4

P+5

Tp, Td

Analog Data In:

ARED

AGRN

ABLUE

CLK

ADCRCLK

ADCSYNC

‘A’ Channel Digital

Data Output

‘B’ Channel Digital

Data Output

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