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ICS1531 Datenblatt(PDF) 37 Page - Integrated Circuit Systems

Teilenummer ICS1531
Bauteilbeschribung  Triple 8-bit MSPS A/D Converters with Line-Locked Clock Generator
PDF  76 Pages
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Hersteller  ICST [Integrated Circuit Systems]
Direct Link  http://www.icst.com
Logo ICST - Integrated Circuit Systems

ICS1531 Datenblatt(HTML) 37 Page - Integrated Circuit Systems

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Chapter 6
Register Set
ICS1531 Rev N 12/1/99
December, 1999
37
Copyright © 1999, Integrated Circuit Systems, Inc.
All rights reserved.
ICS1531 Data Sheet - Preliminary
6.5.15
Register 12h: Rd_Reg
The Rd_Reg (Read Register) is used to read the lock status of the four PLLs on the ICS1531.
6.5.16
Register 13h-1Fh: Reserved
These registers are reserved. (See Section 6.1, “Reserved Bits”.)
Table 6-16.
Rd_Reg Register
Bit
Bit Name
Bit Definition
Ac-
cess
Spec.
Func.
Re-
set
12:7-
12:4
Reserved
Reserved.
Because these bits are read-only:
These bits cannot be programmed.
Information on these bits can be ignored.
Read
N/A
12:3
PNLCLK_Lock
PNLCLK Lock (Status).
0 = The PNLCLK is ‘unlocked’.
1 = The PNLCLK is ‘locked’.
Read
N/A
12:2
MCLK_Lock
MCLK Lock (Status).
0 = The MCLK is ‘unlocked’.
1 = The MCLK is ‘locked’.
Read
N/A
12:1
Pixel PLL_Lock
Pixel Phase-Locked Loop Lock (Status).
0 = The pixel PLL is ‘unlocked’.
1 = The pixel PLL is ‘locked’.
Read
N/A
12:0
DPA_Lock
Dynamic Phase Adjust Lock (Status).
0 = The DPA is ‘unlocked’.
1 = The DPA is ‘locked’.
Read
N/A



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