ICS1531 datasheet(32/76 Pages) ICST

32 / 76 page

ICS1531 Rev N 12/1/99

December, 1999

Chapter 6

ICS1531 Data Sheet - Preliminary

6.5.6

The DPA Control (Dynamic Phase Adjust Control) Register is used to select the resolution of the Dynamic

Phase Adjust circuitry, used to adjust the pixel clock on a sub-pixel basis.

Table 6-8.

DPA Control Register

Bit

Bit Name

Bit Definition

Ac-

cess

Spec.

Func.

Re-

set

05:7-

05:2

Reserved

Reserved.

• See Section 6.1, “Reserved Bits”.

• These bits can be programmed to ‘0’.

––

–

05:1-

05:0

DPA_Res [1-0]

Dynamic Phase Adjust Resolution [1-0].

These bits select the resolution of (that is, the number of delay

element units) for the Dynamic Phase Adjust Offset of Reg

04:5-0.

Table 6-9 lists, for the Reg 05 bit settings:

1. The resulting (decimal) number of delay element units

• 0 = The resolution is for 16 delay element units.

• 1 = The resolution is for 32 delay element units.

•2 = Reserved.

• 3 = The resolution is for 64 delay element units.

2. The corresponding maximum values for Reg 04 DPA offset

3. The corresponding pixel clock output frequency ranges.

Important: (ICS does not recommend using the DPA above

260 MHz.)

R/W

D-DPA

Table 6-9.

DPA Control

Reg 05:1-0

(1) Number of Delay

Element Units

(Decimal)

(2) Reg 04:5-0

Max. Value

(Hex)

(3) Pixel Clock Range

(MHz)

Bit 1

Bit 0

260

130

Reserved

ICS1531 Datenblatt(PDF) 32 Page - Integrated Circuit Systems

ICS1531 Datenblatt(HTML) 32 Page - Integrated Circuit Systems

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76

Datenblatt Download

Link URL