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STM32U595AI Datenblatt(PDF) 295 Page - STMicroelectronics |
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STM32U595AI Datenblatt(HTML) 295 Page - STMicroelectronics |
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295 / 377 page ![]() DS13633 Rev 1 295/377 STM32U59xxx Electrical characteristics 343 Figure 46. ADF timing diagram Table 109. ADF characteristics(1) Symbol Parameter Conditions Min Typ Max Unit fCCKI Input clock frequency via ADF_CCK[1:0] pin, in SLAVE SPI mode 1.71 ≤ VDD ≤ 3.6 V -- 25 MHz fCCKO Output clock frequency in MASTER SPI mode -- 25 fCCKOLF Output clock frequency in LF_MASTER SPI mode -- 5 fSYMB Input symbol rate in Manchester mode -- 20 tHCCKI tLCCKI ADF_CCK[1:0] input clock high and low time In SLAVE SPI mode 2 × Tadf_proc_ck(2) -- ns tHCCKO tLCCKO ADF_CCK[1:0] output clock high and low time In MASTER SPI mode 2 × Tadf_proc_ck -- tHCCKOLF tLCCKOLF ADF_CCK[1:0] output clock high and low time In LF_MASTER SPI mode Tadf_proc_ck - - tSUCCKI Data setup time with respect to ADF_CCK[1:0] input In SLAVE SPI mode: ADF_CCK[1:0] configured in input, measured on rising and falling edge 4.5 - - tHDCCKI Data hold time with respect to ADF_CCK[1:0] input 0- - tSUCCKO Data setup time with respect to ADF_CCK[1:0] output In MASTER SPI mode: ADF_CCK[1:0] configured in output, measured on rising and falling edge 5.5 - - tHDCCKO Data hold time with respect to ADF_CCK[1:0] output 0- - tSUCCKOLF Data setup time with respect to ADF_CCK[1:0] output In LF_MASTER SPI mode: ADF_CCK[1:0] configured in output, measured on rising and falling edge 19.5 - - ns tHDCCKOLF Data hold time with respect to ADF_CCK[1:0] output 0- - 1. Evaluated by characterization. Not tested in production. 2. Tadf_proc_ck is the period of the ADF processing clock. MSv69124V1 ADF_SDIx (I) ADF_CCK (I/O) tSUCCKI tSUCCKO tSUCCKOLF fCCKI, fCCKO, fCCKOLF tLCCKI, tLCCKO, tLCCKOLF tHDCCKI tHDCCKO tHDCCKOLF tHCCKI, tHCCKO, tHCCKOLF tSUCCKI tSUCCKO tSUCCKOLF tHDCCKI tHDCCKO tHDCCKOLF |
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