STM32U595AI datasheet(308/377 Pages) STMICROELECTRONICS

308 / 377 page

Electrical characteristics

STM32U59xxx

308/377

DS13633 Rev 1

5.3.34

FSMC characteristics

Unless otherwise specified, the parameters given in the tables below are derived from tests

performed under the ambient temperature, fHCLK frequency and VDD supply voltage

conditions summarized in Table 32, with the following configuration:

•

Output speed set to OSPEEDRy[1:0] = 10

•

Capacitive load CL = 30 pF, unless otherwise specified

•

Measurement points done at 0.5 × VDD level

•

I/O compensation cell activated

•

HSLV activated when VDD ≤ 2.7 V

•

Voltage scaling range 1

tMAX_COUNT

Maximum possible count with

32-bit counter

65536 × 65536 tTIMxCLK

fTIMxCLK = 160 MHz

26.843

1. TIMx, is used as a general term in which x stands for 1,2,3,4,5,6,7,8,15,16 or 17.

Table 120. TIMx(1) characteristics (continued)

Symbol

Parameter

Conditions

Min

Max

Unit

Table 121. IWDG min/max timeout period at 32 kHz (LSI)(1)

Prescaler divider PR[2:0] bits Min timeout RL[11:0] = 0x000

Max timeout RL[11:0] = 0xFFF

Unit

0.125

512

0.250

1024

/16

0.500

2048

/32

1.0

4096

/64

2.0

8192

/128

4.0

16384

/256

6 or 7

8.0

32768

1. The exact timings still depend on the phasing of the APB interface clock versus the LSI clock, so that there is always a full

RC period of uncertainty.

Table 122. WWDG min/max timeout value at 160 MHz (PCLK)

Prescaler

WDGTB

Min timeout value

Max timeout value

Unit

0.025

1.638

0.051

3.276

0.102

6.553

0.204

13.107

0.409

26.214

0.819

52.428

1.177

75.366

128

3.276

209.715

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