ADAU1761BCPZ-R7 datasheet(45/92 Pages) AD

45 / 92 page

Data Sheet

ADAU1761

PROGRAM RAM, PARAMETER RAM, AND DATA RAM

analog.com

Rev. F | 45 of 92

Table 26. RAM Map and Read/Write Modes

Memory

Size

Address Range

Read

Write

Write Modes

Parameter RAM

1024 × 32

0 to 1023 (0x0000 to 0x03FF)

Yes

Direct, safeload

Program RAM

1024 × 40

2048 to 3071 (0x0800 to 0x0BFF)

Yes

Direct

Table 26 shows the RAM map (the ADAU1761 register map is

provided in the Control Registers section). The address space en-

compasses a set of registers and three RAMs: program, parameter,

and data. The program RAM and parameter RAM are not initialized

on power-up and are in an unknown state until written to.

PROGRAM RAM

The program RAM contains the 40-bit operation codes that are exe-

cuted by the core. The SigmaStudio compiler calculates maximum

instructions per frame for a project and generates an error when the

value exceeds the maximum allowable instructions per frame based

on the sample rate of the signals in the core.

Because the end of a program contains a jump-to-start command,

the unused program RAM space does not need to be filled with

no-operation (NOP) commands.

PARAMETER RAM

The parameter RAM is 32 bits wide and occupies Address 0 to

Address 1023. Each parameter is padded with four 0s before the

MSB to extend the 28-bit word to a full 4-byte width. The data

format of the parameter RAM is twos complement, 5.23. This

means that the coefficients can range from +16.0 (minus 1 LSB)

to −16.0, with 1.0 represented by the binary word 0000 1000 0000

0000 0000 0000 0000 or by the hexadecimal word 0x00 0x80 0x00

0x00.

The parameter RAM can be written to directly or with a safe-load

write. The direct write mode of operation is typically used during a

complete new loading of the RAM using burst mode addressing to

avoid any clicks or pops in the outputs. Note that this mode can

be used during live program execution, but because there is no

handshaking between the core and the control port, the parameter

RAM is unavailable to the DSP core during control writes, resulting

in pops and clicks in the audio stream.

SigmaStudio automatically assigns the first eight positions to safe-

load parameters; therefore, project-specific parameters start at Ad-

dress 0x0008.

The parameter RAM should not be written to until the DSPEN bit

has been set in Register R61 (Address 0x40F5).

DATA RAM

The ADAU1761 data RAM is used to store audio data-words for

processing, as well as certain run-time parameters. SigmaStudio

provides the data and address information for writing to and reading

from the data RAM.

When implementing blocks, such as delays, that require large

amounts of data RAM space, data RAM utilization should be taken

into account. The SigmaDSP core processes delay times in one-

sample increments; therefore, the total pool of delay available to the

user equals 4096 multiplied by the sample period. For a fS,DSP of

48 kHz, the pool of available delay is a maximum of about 86 ms,

where fS,DSP is the DSP core sampling rate. In practice, this much

data memory is not available to the user because every block in a

design uses a few data memory locations for its processing. In most

DSP programs, this does not significantly affect the total delay time.

The SigmaStudio compiler manages the data RAM and indicates

whether the number of addresses needed in the design exceeds

the maximum number available.

READ/WRITE DATA FORMATS

The read/write formats of the control port are designed to be byte

oriented to allow for easy programming of common micro-controller

chips. To fit into a byte-oriented format, 0s are added to the data

fields before the MSB to extend the data-word to eight bits. For

example, 28-bit words written to the parameter RAM are preceded

by four leading 0s to equal 32 bits (four bytes); 40-bit words

written to the program RAM are not preceded by 0s because they

are already a full five bytes. These zero-padded data fields are

appended to a 3-byte field consisting of a 7-bit chip address, a

read/write bit, and a 16-bit RAM/register address. The control port

knows how many data bytes to expect based on the address given

in the first three bytes.

The total number of bytes for a single-location write command can

vary from one byte (for a control register write) to five bytes (for

a program RAM write). Burst mode can be used to fill contiguous

the address and data of the first RAM or register location to be

written. Rather than ending the control port transaction (by issuing

a stop command in I2C mode or by bringing the CLATCH signal

high in SPI mode after the data-word), as would be done in a

single-address write, the next data-word can be written immediately

without specifying its address. The ADAU1761 control port auto-

increments the address of each write even across the boundaries

of the different RAMs and registers. Table 28 and Table 30 show

examples of burst mode writes.

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