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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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ADAU1761BCPZ-R7 Datenblatt(PDF) 23 Page - Analog Devices |
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ADAU1761BCPZ-R7 Datenblatt(HTML) 23 Page - Analog Devices |
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23 / 92 page  Data Sheet ADAU1761 STARTUP, INITIALIZATION, AND POWER analog.com Rev. F | 23 of 92 Case 2: PLL Is Used The core clock to the entire chip is off during the PLL lock acquisi- tion period. The user can poll the lock bit to determine when the PLL has locked. After lock is acquired, the ADAU1761 can be started by asserting the core clock enable bit (COREN) in Register R0 (clock control register, Address 0x4000). This bit enables the core clock to all the internal blocks of the ADAU1761. PLL Lock Acquisition During the lock acquisition period, only Register R0 (Address 0x4000) and Register R1 (Address 0x4002) are accessible through the control port. Because all other registers require a valid main clock for reading and writing, do not attempt to access any other register. Any read or write is prohibited until the core clock enable bit (COREN) and the lock bit are both asserted. To program the PLL during initialization or reconfiguration of the clock setting, the following procedure must be followed: 1. Power down the PLL. 2. Reset the PLL control register. 3. Start the PLL. 4. Poll the lock bit. 5. Assert the core clock enable bit after the PLL lock is acquired. The PLL control register (Register R1, Address 0x4002) is a 48‑bit register where all bits must be written with a single continuous write to the control port. |
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