ADAU1761BCPZ-R7 datasheet(51/92 Pages) AD

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Data Sheet

ADAU1761

CONTROL REGISTERS

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Rev. F | 51 of 92

Table 35. Clock Control Register (Continued)

Bits

Bit Name

Description

Setting

Input Clock Frequency

256 × fS (default)

512 × fS

768 × fS

1024 × fS

COREN

Core clock enable. Only the R0 and R1 registers can be accessed when this bit is set to 0 (core clock disabled).

0 = core clock disabled (default).

1 = core clock enabled.

R1: PLL Control, 16,386 (0x4002)

Table 36.

Byte

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

M[15:8]

M[7:0]

N[15:8]

N[7:0]

Reserved

R[3:0]

X[1:0]

Type

Reserved

Lock

PLLEN

Table 37. PLL Control Register

Byte

Bits

Bit Name

Description

[7:0]

M[15:8]

PLL denominator MSB. This value is concatenated with M[7:0] to make up a 16-bit number.

[7:0]

M[7:0]

PLL denominator LSB. This value is concatenated with M[15:8] to make up a 16-bit number.

M[15:8] (MSB)

M[7:0] (LSB)

Value of M

00000000

…

00000000

11111101

253 (default)

…

11111111

65,535

[7:0]

N[15:8]

PLL numerator MSB. This value is concatenated with N[7:0] to make up a 16-bit number.

[7:0]

N[7:0]

PLL numerator LSB. This value is concatenated with N[15:8] to make up a 16-bit number.

N[15:8] (MSB)

N[7:0] (LSB)

Value of N

00000000

…

00000000

00001100

12 (default)

…

11111111

65,535

[6:3]

R[3:0]

PLL integer setting.

Setting

Value of R

0010

2 (default)

0011

0100

0101

0110

0111

1000

[2:1]

X[1:0]

PLL input clock divider.

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