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ADAU1761BCPZ-R7 Datenblatt(PDF) 82 Page - Analog Devices

Teilenummer ADAU1761BCPZ-R7
Bauteilbeschribung  SigmaDSP Stereo, Low Power, 96 kHz, 24-Bit Audio Codec with Integrated PLL
PDF  92 Pages
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Hersteller  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADAU1761BCPZ-R7 Datenblatt(HTML) 82 Page - Analog Devices

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Data Sheet
ADAU1761
CONTROL REGISTERS
analog.com
Rev. F | 82 of 92
Table 144. Serial Port Sampling Rate Register (Continued)
Bits
Bit Name
Description
100
fS/2
24 kHz
101
fS/1.5
32 kHz
110
fS/0.5
96 kHz
111
Reserved
R65: Clock Enable 0, 16,633 (0x40F9)
This register disables or enables the digital clock engine for different blocks within the ADAU1761. For maximum power saving, use this register
to disable blocks that are not being used.
Table 145.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
SLEWPD
ALCPD
DECPD
SOUTPD
INTPD
SINPD
SPPD
Table 146. Clock Enable 0 Register
Bits
Bit Name
Description
6
SLEWPD
Codec slew digital clock engine enable. When powered down, the analog playback path volume controls are disabled and stay set to their
current state.
0 = powered down (default).
1 = enabled.
5
ALCPD
ALC digital clock engine enable.
0 = powered down (default).
1 = enabled.
4
DECPD
Decimator resync (dejitter) digital clock engine enable.
0 = powered down (default).
1 = enabled.
3
SOUTPD
Serial routing outputs digital clock engine enable.
0 = powered down (default).
1 = enabled.
2
INTPD
Interpolator resync (dejitter) digital clock engine enable.
0 = powered down (default).
1 = enabled.
1
SINPD
Serial routing inputs digital clock engine enable.
0 = powered down (default).
1 = enabled.
0
SPPD
Serial port digital clock engine enable.
0 = powered down (default).
1 = enabled.
R66: Clock Enable 1, 16,634 (0x40FA)
This register enables Digital Clock Generator 0 and Digital Clock Generator 1. Digital Clock Generator 0 generates sample rates for the ADCs,
DACs, and DSP. Digital Clock Generator 1 generates BCLK and LRCLK for the serial port when the part is in main mode. For maximum power
saving, use this register to disable clocks that are not being used.
Table 147.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
CLK1
CLK0



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