ADAU1761BCPZ-R7 datasheet(77/92 Pages) AD

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Data Sheet

ADAU1761

CONTROL REGISTERS

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Rev. F | 77 of 92

port control mode, the pins are set through writes to memory locations described in Table 32. The value of the optional internal pull-up is

nominally 250 kΩ.

The output CRC error and output watchdog error settings are sticky, that is, once set, they remain set until the ADAU1761 is reset.

Table 124.

Address

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x40C6

Reserved

GPIO0[3:0]

0x40C7

Reserved

GPIO1[3:0]

0x40C8

Reserved

GPIO2[3:0]

0x40C9

Reserved

GPIO3[3:0]

Table 125. GPIO Pin Functionality Bit Settings

GPIOx[3:0] Bits

GPIO Pin Function

0000

Input without debounce (default)

0001

Input with debounce (0.3 ms)

0010

Input with debounce (0.6 ms)

0011

Input with debounce (0.9 ms)

0100

Input with debounce (5 ms)

0101

Input with debounce (10 ms)

0110

Input with debounce (20 ms)

0111

Input with debounce (40 ms)

1000

Input controlled by I2C/SPI port

1001

Output set by I2C/SPI port, with pull-up

1010

Output set by I2C/SPI port, no pull-up

1011

Output set by DSP core, with pull-up

1100

Output set by DSP core, no pull-up

1101

Reserved

1110

Output CRC error (sticky)

1111

Output watchdog error (sticky)

Table 126. GPIO Pin Control Registers

Address

Bit Name

Description

Decimal

Hex

R48

16,582

0x40C6

GPIO0[3:0]

GPIO 0 pin function (see Table 125)

R49

16,583

0x40C7

GPIO1[3:0]

GPIO 1 pin function (see Table 125)

R50

16,584

0x40C8

GPIO2[3:0]

GPIO 2 pin function (see Table 125)

R51

16,585

0x40C9

GPIO3[3:0]

GPIO 3 pin function (see Table 125)

R52 to R56: Watchdog Registers, 16,592 to 16,596 (0x40D0 to 0x40D4)

A program counter watchdog is used when the core does block processing (which can span several samples). The watchdog flags an error if

the program counter reaches a specific 24-bit value (ranging from 0x000000 to 0xFFFFFF) that is set in the register map. This value consists of

three consecutive 8-bit register locations. The error flag sends a high signal to one of the GPIO pins. The watchdog function must be enabled

by setting the DOGEN bit high in Register R52 (Address 0x40D0).

The watchdog error bit (DOGER) is the 1-bit watchdog error flag that can be sent to a GPIO pin, as described in Table 125. This error flag can

connect, for example, to an interrupt pin on a microcontroller in the system. The flag is reset when the DOGEN bit goes low. This flag can also

be read back over the control port from Register R56 (Address 0x40D4).

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