ADAU1761BCPZ-R7 datasheet(57/92 Pages) AD

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Data Sheet

ADAU1761

CONTROL REGISTERS

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Rev. F | 57 of 92

Table 53. Right Differential Input Volume Control Register (Continued)

Bits

Bit Name

Description

RDEN

Right differential PGA enable. When enabled, the RINP and RINN pins are used as a full differential pair. When disabled, these two pins are

configured as two single-ended inputs with the signals routed around the PGA.

0 = disabled (default).

1 = enabled.

R10: Record Microphone Bias Control, 16,400 (0x4010)

This register controls the MICBIAS pin settings for biasing electret type analog microphones.

Table 54.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reserved

MPERF

MBI

Reserved

MBIEN

Table 55. Record Microphone Bias Control Register

Bits

Bit Name

Description

MPERF

Microphone bias is enabled for high performance or normal operation. High performance operation sources more current to the microphone.

0 = normal operation (default).

1 = high performance.

MBI

Microphone voltage bias as a fraction of AVDD.

0 = 0.90 × AVDD (default).

1 = 0.65 × AVDD.

MBIEN

Enables the MICBIAS output.

0 = disabled (default).

1 = enabled.

R11: ALC Control 0, 16,401 (0x4011)

Table 56.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PGASLEW[1:0]

ALCMAX[2:0]

ALCSEL[2:0]

Table 57. ALC Control 0 Register

Bits

Bit Name

Description

[7:6]

PGASLEW[1:0]

PGA volume slew time when the ALC is off. The slew time is the period of time that a volume increase or decrease takes to ramp up or

ramp down to the target volume set in Register R8 (left differential input volume control) and Register R9 (right differential input volume

control).

Setting

Slew Time

24 ms (default)

48 ms

96 ms

Off

[5:3]

ALCMAX[2:0]

The maximum ALC gain sets a limit to the amount of gain that the ALC can provide to the input signal. This protects small signals from

excessive amplification.

Setting

Maximum ALC Gain

000

−12 dB (default)

001

−6 dB

010

0 dB

011

6 dB

100

12 dB

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