ADAU1761BCPZ-R7 datasheet(75/92 Pages) AD

75 / 92 page

Data Sheet

ADAU1761

CONTROL REGISTERS

analog.com

Rev. F | 75 of 92

R41: Control Port Pad Control 1, 16,432 (0x4030)

With IOVDD set to 3.3 V, the low and high drive strengths of the SDA/COUT pin are approximately 2.0 mA and 4.0 mA, respectively. With

IOVDD set to 1.8 V, the low and high drive strengths are approximately 0.8 mA and 1.7 mA, respectively. The high drive strength mode may be

useful for generating a stronger ACK pulse in I2C mode, if needed.

Table 116.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reserved

SDASTR

Table 117. Control Port Pad Control 1 Register

Bits

Bit Name

Description

SDASTR

SDA/COUT pin drive strength.

0 = low (default).

1 = high.

R42: Jack Detect Pin Control, 16,433 (0x4031)

With IOVDD set to 3.3 V, the low and high drive strengths of the JACKDET/MICIN pin are approximately 2.0 mA and 4.0 mA, respectively.

With IOVDD set to 1.8 V, the low and high drive strengths are approximately 0.8 mA and 1.7 mA, respectively. The optional pull-up/ pull-down

resistors are nominally 250 kΩ. When enabled, these pull-up/pull-down resistors set the input signals to a defined state when the signal source

becomes three-state.

Table 118.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reserved

JDSTR

Reserved

JDP[1:0]

Reserved

Table 119. Jack Detect Pin Control Register

Bits

Bit Name

Description

JDSTR

JACKDET/MICIN pin drive strength.

0 = low (default).

1 = high.

[3:2]

JDP[1:0]

JACKDET/MICIN pad pull-up/pull-down configuration.

Setting

Configuration

Pull-up

Reserved

None (default)

Pull-down

R67: Dejitter Control, 16,438 (0x4036)

The dejitter control register allows the size of the dejitter window to be set, and also allows all dejitter circuits in the device to be activated

or bypassed. Dejitter circuits protect against duplicate samples or skipped samples due to jitter from the serial ports in subordinate mode.

Disabling and reenabling certain subsystems in the device—that is, the ADCs, serial ports, SigmaDSP core, and DACs—during operation can

cause the associated dejitter circuits to fail. As a result, audio data fails to be output to the next subsystem in the device.

When the serial ports are in main mode, the dejitter circuit can be bypassed by setting the dejitter window to 0. When the serial ports are in

subordinate mode, the dejitter circuit can be reinitialized prior to outputting audio from the device, guaranteeing that audio is output to the next

subsystem in the device. Any time that audio must pass through the ADCs, serial port, sound engine/DSP core, or DACs, the dejitter circuit can

be bypassed and reset by setting the dejitter window size to 0. In this way, the dejitter circuit can be immediately reactivated, without a wait

period, by setting the dejitter window size to the default value of 3.

ADAU1761BCPZ-R7 Datenblatt(PDF) 75 Page - Analog Devices

ADAU1761BCPZ-R7 Datenblatt(HTML) 75 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92

Datenblatt Download

Link URL