ADAU1761BCPZ-R7 datasheet(78/92 Pages) AD

78 / 92 page

Data Sheet

ADAU1761

CONTROL REGISTERS

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Rev. F | 78 of 92

Table 127.

Address

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x40D0

Reserved

DOGEN

0x40D1

DOG[23:16]

0x40D2

DOG[15:8]

0x40D3

DOG[7:0]

0x40D4

Reserved

DOGER

Table 128. Watchdog Registers

Address

Bit Name

Description

Decimal

Hex

R52

16,592

0x40D0

DOGEN

Watchdog enable bit.

0 = disabled (default).

1 = enabled.

R53

16,593

0x40D1

DOG[23:16]

Watchdog value, Bits[23:16] (MSB).

R54

16,594

0x40D2

DOG[15:8]

Watchdog value, Bits[15:8].

R55

16,595

0x40D3

DOG[7:0]

Watchdog value, Bits[7:0].

DOG[23:16]

DOG[15:8]

DOG[7:0]

Hex Value

00000000

0x000000 (default)

…

11111111

0xFFFFFF

R56

16,596

0x40D4

DOGER

Watchdog error (read-only bit).

0 = no error (default).

1 = error.

R57: DSP Sampling Rate Setting, 16,619 (0x40EB)

Table 129.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reserved

DSPSR[3:0]

Table 130. DSP Sampling Rate Setting Register

Bits

Bit Name

Description

[3:0]

DSPSR[3:0]

SigmaDSP core sampling rate. The DSP sampling rate is a ratio of the base sampling rate, fS. The base sampling rate is determined by the

operating frequency of the core clock. For most applications, the SigmaDSP core sampling rate should equal the converter sampling rate

(set using the CONVSR[2:0] bits in Register R17) and the serial port sampling rate (set using the SPSR[2:0] bits in Register R64).

Setting

Sampling Rate

Base Sampling Rate (fS = 48 kHz)

0000

fS/0.5

96 kHz, base

0001

48 kHz (default)

0010

fS/1.5

32 kHz

0011

fS/2

24 kHz

0100

fS/3

16 kHz

0101

fS/4

12 kHz

0110

fS/6

8 kHz

0111

Serial input data rate

1000

Serial output data rate

1111

None

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