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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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AM79C976 Datenblatt(PDF) 34 Page - Advanced Micro Devices |
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AM79C976 Datenblatt(HTML) 34 Page - Advanced Micro Devices |
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34 / 309 page  34 Am79C976 8/01/00 P R E L I M INARY access is a memory cycle. DEVSEL is asserted two clock cycles after the host has asserted FRAME. See Figure 11 and Figure 22. )LJXUH 6ODYH &RQILJXUDWLRQ5HDG )LJXUH 6ODYH&RQILJXUDWLRQ:ULWH For compatibility with older members of the PCnet family of controllers, the 32 lowest addresses of the I/O or memory space claimed by the Am79C976 device sup- port indirect addressing of internal registers. The Am79C976 controller does not support burst transfers for access to these locations. When the host keeps FRAME asserted for a second data phase in this ad- dress range, the Am79C976 controller will disconnect the transfer. However, the controller does support burst accesses to locations at offsets 32 and above. Because of the side effects of reading the Reset Reg- ister at offset 14h or 18h (depending on the state of DWIO (CMD2, bit 28)), locations at offsets less than 20h cannot be prefetched. The Am79C976 controller supports fast back-to-back transactions to different targets. This is indicated by the Fast Back-To-Back Capable bit (PCI Status register, bit 7), which is hardwired to 1. The Am79C976 controller is capable of detecting an I/O or a memory-mapped I/O cycle even when its address phase immediately fol- lows the data phase of a transaction to a different target, without any idle state in-between. There will be no con- tention on the DEVSEL, TRDY, and STOP signals, since the Am79C976 controller asserts DEVSEL on the sec- ond clock after FRAME is asserted (medium timing). See Figure 33 and Figure 44. 6 FRAME CLK AD IRDY TRDY C/BE DEVSEL STOP IDSEL 1 23456 1010 PAR PAR PAR BE DATA ADDR 7 22929B3 FRAME CLK AD IRDY TRDY C/BE DEVSEL STOP IDSEL 1 23456 1011 PAR PAR PAR BE DATA ADDR 7 22929B4 The Am79C976 controller will not assert DEVSEL if it detects an address match, but the PCI command is not of the correct type. In memory mapped I/O mode, the Am79C976 controller aliases all accesses to the I/O re- sources of the command types Memory Read Multiple and Memory Read Line to the basic Memory Read command. All accesses of the type Memory Write and Invalidate are aliased to the basic Memory Write com- mand. Eight-bit, 16-bit, and 32-bit transactions are sup- ported. The Am79C976 controller decodes all 32 address lines to determine which I/O resource is ac- cessed. The number of wait states added to slave transactions varies. Typical values are shown in the table below: Slave Transactions Transaction Type Read Write Memory-mapped transactions 90 I/O-mapped transactions 9 3 |
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