AM79C976 datasheet(64/309 Pages) AMD

64 / 309 page

Am79C976

8/01/00

P R E L I M INARY

Receive descriptor polling will continue even if transmit

polling is disabled by setting TXDPOLL. If at least two

receive descriptors are owned by the Am79C976 con-

troller there will be no descriptor polling if there is no

network activity.

The user may change the poll time value from the de-

fault value by modifying the value in the Transmit Poll-

ing Interval register (CSR47). The default value is

0000h, which corresponds to a polling interval of

65,536 X 3 ERCLK clock periods or 2.185 ms when

ERCLK = 90 MHz.

When the Am79C976 controller is in the process of re-

ceiving a frame and it does not own the next descriptor

or if it is in the process of transmitting a frame that does

not end in the current descriptor and it does not own the

next descriptor, it switches to the chain polling mode in

which the polling interval is determined by the Chain

Polling Interval register (CSR49). Thus, the device can

be programmed to poll at a faster rate when it is about

to run out of buffers.

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If, after a transmit descriptor access, the Am79C976

controller finds that the OWN bit of that descriptor is not

set, the Am79C976 controller resumes the poll time

count and re-examines the same descriptor at the next

expiration of the poll time count.

If the OWN bit of the descriptor is set, but the Start of

Packet (STP) bit is not set, the Am79C976 controller

will immediately request the bus in order to clear the

OWN bit of this descriptor. After resetting the OWN bit

of this descriptor, the Am79C976 controller will again

immediately request the bus in order to access the next

descriptor in the ring.

If the OWN bit is set and the buffer length is 0, the OWN

bit will be cleared. The Am79C976 controller skips buff-

ers with length of 0, which differs from the C-LANCE

device, which interprets a buffer length of 0 to mean a

4096-byte buffer. For the Am79C976 device a zero

length buffer is acceptable anywhere in the buffer

chain.

If the OWN bit and STP are set, the DMA controller will

start reading data from the current transmit buffer. If the

next transmit descriptor is not already known to be

owned, the Am79C976 controller will interleave a read

of this descriptor into the sequence of data DMA oper-

ations.

If the next transmit descriptor has the OWN bit set, the

Am79C976 controller will complete reading the data

from the current transmit buffer, clear the OWN bit in

the current descriptor and advance the internal ring

pointer to make the next transmit descriptor the new

current transmit descriptor.

The Am79C976 controller returns ownership of trans-

mit descriptors to the software when the DMA transfer

of data from system memory to the Am79C976 control-

ler’s memory is complete. This is different from older

devices in the PCnet family, which will not return the

last transmit descriptor of a frame (the one with

ENP=1) until transmission of the frame is complete.

The Am79C976 controller does not return any status

information in the transmit descriptor, it will only write to

the OWN bit to clear it.

Normally, the driver will set all the OWN bits of a frame

in reverse order so that the Am79C976 controller will

never encounter the situation where the current trans-

mit descriptor has OWN=1 and ENP=0 and the next

transmit descriptor has OWN=0. Older devices in the

PCnet family treat this condition as a fatal error. The

Am79C976 controller allows this mode of operation to

permit DMA of the beginning of a frame before pro-

cessing of the entire frame is complete. The number of

bytes in the first buffer(s) should be less than the trans-

mit start point or the REX_UFLO bit in CMD3 should be

set.

When the Am79C976 controller encounters the condi-

tion of the current transmit descriptor’s OWN=1 and

ENP=0 and the next transmit descriptor’s OWN=0, it

enters the chain polling mode. In this mode, polling of

the descriptor will occur at intervals determined by the

Chain Polling Interval register (CSR49). Setting the

TDMD bit will also cause a poll. Chain polling may be

disabled by setting the CHDPOLL bit in CSR7 or

CMD2. Note that this will also disable chain polling for

receive descriptors.

If underflow occurs due to delays in setting the OWN

bits or excessive bus latency, the transmitter will ap-

pend an inverted FCS field to the frame and will incre-

ment the XmtUnderrunPkts counter. The frame may be

retransmitted (if the REX_UFLO bit in CMD3 is set) or

discarded.

If an error occurs in the transmission that causes the

frame to be discarded (late collision, underflow or retry

failure with the corresponding retry or retransmit option

not enabled) before the entire frame has been trans-

ferred or if the current transmit descriptor has its KILL

bit set, and if current transmit descriptor does not have

its ENP bit set, the Am79C976 controller will skip over

the rest of the frame which experienced the error. The

Am79C976 controller will clear the OWN bit for all de-

scriptors with OWN = 1 and STP = 0 and continue in

like manner until a descriptor with OWN = 0 (no more

transmit frames in the ring) or OWN = 1 and STP = 1

(the first buffer of a new frame) is reached.

At the end of any transmit operation, whether success-

ful or with errors, the Am79C976 controller will always

perform another polling operation, unless the next

transmit descriptor is already known to be owned.

AM79C976 Datenblatt(PDF) 64 Page - Advanced Micro Devices

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