AM79C976 datasheet(45/309 Pages) AMD

45 / 309 page

8/01/00

Am79C976

P R E L I M INARY

ample, the memory system extends the data phase of

the first access by one wait state. The following three

data phases take one clock cycle each, which is deter-

mined by the timing of TRDY.

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The BIU has two programmable features that can im-

prove the DMA performance with PCI bridges that do

not automatically stop burst transfers to align them with

cache line boundaries:

1. The Burst Alignment (BA) bit (CTRL0, bit 0). When

this bit is set, if a burst transfer starts in the middle

of a cache line, the transfer will stop at the first

cache line boundary.

2. The Burst Limit Register (CTRL0, bits 3:0). This 4-

bit register limits the maximum length of a burst

transfer. If the contents of this register are 0, the

burst length is limited by the amount of data avail-

able or by the amount of FIFO space available.

If the contents of this register are not zero, a burst

transfer will end when the transfer has crossed the

number of cache line boundaries equal to the con-

tents of this register.

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When the Am79C976 controller is a bus master, the cy-

cles it produces on the PCI bus may be terminated by

the target in one of three different ways: disconnect

with data transfer, disconnect without data transfer, and

target abort.

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Figure 15 shows a disconnection in which one last data

transfer occurs after the target asserted STOP. STOP

is asserted on clock 4 to start the termination se-

quence. Data is still transferred during this cycle, since

both IRDY and TRDY are asserted. The Am79C976

controller terminates the current transfer with the deas-

sertion of FRAME on clock 5 and of IRDY one clock

later. It finally releases the bus on clock 7. The

Am79C976 controller will again request the bus after

two clock cycles, if it wants to transfer more data. The

starting address of the new transfer will be the address

of the next non-transferred data.

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FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

REQ

GNT

2345678

ADDR

DATA

0111

PAR

DATA

PAR

DEVSEL is sampled

22929B16

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