AM79C976 datasheet(94/309 Pages) AMD

94 / 309 page

Am79C976

8/01/00

P R E L I M INARY

BASE can be programmed to 0 or 1 through PCI con-

figuration space accesses to ROMBASE.

Bit 0 of ROM_CFG controls bit 0 of ROMBASE. If bit 0

of ROM_CFG is 0, the host CPU cannot write to bit 0 of

ROMBASE. This bit is the address decode enable bit.

When this bit is fixed at 0, it will appear to the host CPU

that the ROM Base Address Register and, therefore,

the expansion ROM does not exist.

If bit 0 of ROM_CFG is set to 1, the host CPU is able to

read and write bit 0 of ROMBASE.

As an example, if the Expansion ROM occupies 216

(65536) bytes, bits 15:9 of ROMBASE should be fixed

at 0. Since bits 15:9 of ROMBASE are controlled by bits

7:1 of ROM_CFG, bits 7:1 of ROM_CFG should be

cleared to 0 and bits 15:8 should be set to 1. To make

ROMBASE accessible to the host CPU, bit 0 of

ROM_CFG should be set to 1. Therefore, ROM_CFG

should be set to FF01h. If the host CPU writes all 1s to

the ROMBASE register and then reads back the con-

tents of ROMBASE, the result would be FFFF0001h.

After the host CPU has written to the Expansion ROM

Base Address Register in PCI configuration space to

map the ROM into PCI memory space and to enable

accesses to the ROM, the address output to the Expan-

sion ROM will be the offset from the address on the PCI

bus to ROMBASE.

The Am79C976 controller aliases all accesses to the

Expansion ROM of the command types Memory Read

Multiple and Memory Read Line to the basic Memory

Read command.

Since setting MEMEN also enables memory mapped

access to the I/O resources, attention must be given to

the PCI Memory Mapped I/O Base Address register,

before enabling access to the Expansion ROM. The

host must set the PCI Memory Mapped I/O Base Ad-

dress register to a value that prevents the Am79C976

controller from claiming any memory cycles not in-

tended for it.

During the boot procedure, the system will try to find an

Expansion ROM. A PCI system assumes that an Ex-

pansion ROM is present when it reads the ROM signa-

ture 55h (byte 0) and AAh (byte 1).

'LUHFW)ODVK $FFHVV

In addition to mapping the Flash memory into PCI ad-

dress space, the Am79C976 controller provides an in-

direct read/write data path for programming the Flash

memory. The Flash is accessed by first writing the

memory address to the Flash Address Register, and

then reading or writing the Flash Data Register.

For software compatibility with older PCnet devices, the

Flash device can also be accessed by a read or write

to the Expansion Bus Data port (BCR30). The user

must load the upper address EPADDRU (BCR 29, bits

3-0). EPADDRU is not needed if the Flash size is 64K

or less, but still must be programmed. The user will

then load the lower 16 bits of address, EPADDRL (BCR

28, bits 15-0).

)ODVK(3520 5HDG

A read to the Flash Data Register will start a read cycle

on the External Memory Interface. The Am79C976

controller will drive ERD[11:8] with the 4 most signifi-

cant address bits at the same time that it drives

ERA[19:0] with the 20 least significant bits.

The FLCS pin is driven low for the value ROMTMG + 1.

Figure 38 assumes that ROMTMG is set to nine.

ERD[7:0] is sampled with the next rising edge of CLK

ten clock cycles after ERA[19:0] was driven with a new

address value. This PCI slave access to the Flash/

EPROM will result in a retry for the very first access.

Subsequent accesses may give a retry or not, depend-

ing on whether or not the data is present and valid. The

access time is dependent on the ROMTMG bits

(CTRL0, bits 11-8, or BCR18, bits 15-12) and can be

tuned for the particular memory device used.

This access mechanism using BCR28, 29, and 30 dif-

fers from the Expansion ROM access mechanism

since only one byte is read in this manner, instead of

the 4 bytes in an Expansion ROM access.

If the Lower Address Auto Increment (LAAINC) bit

(FLASH_ADDR, bit 31 or BCR29, bit 14) is set, the

EBADDRL address will be incremented and a continu-

ous series of reads from the Expansion Data Port

(FLASH_DATA or EBDATA, BCR30) is possible. The

upper address field, EBADDRU, is not automatically

incremented when the lower address field, EBADDRL

rolls over.

The Flash write procedure is almost identical to the

read access, except that the Am79C976 controller will

not drive FLOE low. The FLCS and FLWE signals are

driven low for the value ROMTMG again. The write to

the FLASH port is a posted write and will not result in a

retry to the PCI, unless the host tries to write a new

value before the previous write is complete. Then the

host will experience a retry. See Figure 3939.

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