AM79C976 datasheet(90/309 Pages) AMD

90 / 309 page

Am79C976

8/01/00

P R E L I M INARY

elapsed since the first interrupt event occurred. The

use of the Delayed Interrupt Register allows the inter-

rupt service routine to process several events at one

time without having to return control back to the oper-

ating system between events.

A receive interrupt event occurs when receive inter-

rupts are enabled, and the Am79C976 device has com-

pleted the reception of a frame and has updated the

frame’s descriptors. A receive interrupt event causes

the Receive Interrupt (RINT) bit in CSR0 to be set if it

is not already set. Similarly, a transmit interrupt event

occurs when transmit interrupts are enabled, and the

Am79C976 device has copied a transmit frame’s data

to the transmit FIFO and has updated the frame’s de-

scriptors. A transmit interrupt event causes the Trans-

mit Interrupt (TINT) bit in CSR0 to be set if it is not

already set. Note that frame receptions or transmis-

sions affect the interrupt event counter only when re-

ceive or transmit interrupts are enabled.

The Delayed Interrupt Register contains the 5-bit Event

Count field and the 11-bit Maximum Delay Time field.

Each time the host CPU clears the RINT or TINT bit,

the contents of the Event Count field are loaded into an

internal interrupt event counter, the contents of the

Maximum Delay Time field are loaded into an internal

interrupt event timer, and the interrupt event timer is

disabled. Each time a receive or transmit interrupt

event occurs, the interrupt event counter is decre-

mented by 1 and the interrupt event timer is enabled, or

if it has already been enabled, it continues to count

down. Once the interrupt event timer has been en-

abled, it decrements by 1 every 10 microseconds.

When either the interrupt event counter or the interrupt

event timer reaches zero, the INTA pin is asserted.

External Address Detection Interface

The EADI is provided to allow external address filtering

and to provide a Receive Frame Tag word for propri-

etary routing information. This feature is typically uti-

lized by terminal servers, switches and/or router

products. The EADI interface can be used in conjunc-

tion with external logic to capture the packet destination

address from the MII input data stream as it arrives at

the Am79C976 controller, to compare the captured ad-

dress with a table of stored addresses or identifiers,

and then to determine whether or not the Am79C976

controller should accept the packet.

The EADI consists of the External Address Reject

(EAR), Start Frame-Byte Delimiter (SFBD), Receive

Frame Tag Data (RXFRTGD), and Receive Frame Tag

Enable (RXFRTGE) pins.

The SFBD pin indicates two types of information to the

external logic--the start of the frame and byte bound-

aries. The first low-to-high transition on the SFBD pin

after the assertion of the RX_DV signal indicates that

the first nibble of the Destination Address field of the in-

coming frame is available on the RXD[3:0] pins. There-

after, SFBD toggles with each RX_CLK pulse so that

SFBD is high when the least significant nibble of frame

date is present on the RXD[3:0] lines and low when the

most significant nibble is present. SFBD stays low

when RX_DV is not asserted (which indicates that the

receiver is idle).

Note that the SFBD signal is available on any LED pin.

To direct the SFBD signal to one of the LED pins, the

SFBDE and LEDPOL bits should be set to 1 and the

PSE bit should be cleared to 0 in the appropriate LED

pin, the LEDPOL bit sets the polarity to active high and

enables the totem-pole driver, and the PSE bit disables

the LED pulse stretcher logic.

If the system needs all four LEDs as well as the EADI

function, the Am79C976 controller can be programmed

to use the shared pin for the LED function, and the ex-

ternal logic can be designed to generate the SFBD sig-

nal by searching for the 11010101b Star t Frame

Delimiter (SFD) pattern in the RCD[3:0] data.

The external address detection logic can use the EAR

input to indicate whether or not the incoming frame

should be accepted. If the EAR signal remains high

during the receive protect time, the frame will be ac-

cepted and copied into host system memory. The re-

ceive protect time is a period of time measured from the

receipt of the SFD field of a frame. The length of the re-

ceive protect time is programmable through the Re-

ceive Protect Register.

A frame is accepted if it passes either the internal ad-

dress match criteria or the external address match cri-

teria. If the internal address logic is disabled, the

acceptance of a frame depends entirely on the external

address match logic. If the external address match

logic is disabled, the acceptance of a frame depends

entirely on the internal address match logic.

Internal address match is disabled when PROM

(CSR15, bit 15) is cleared to 0, DRCVBC (CSR15, bit

14) and DRCVPA (CSR15, bit 13) are set to 1, and the

Logical Address Filter registers (CSR8 to CSR11) are

programmed to all zeros.

External address matching can be disabled by holding

the EAR pin low. There is no programmable bit that

causes the Am79C976 device to ignore the state of the

EAR pin.

The EADI logic only samples EAR from 2 nibble times

after SFD until the end of the receive protect time. (See

the Receive Protect Register section.) The frame will

be accepted if EAR has not been asserted during this

window. EAR must have a pulse width of at least two bit

times plus 10 ns.

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