AM79C976 datasheet(60/309 Pages) AMD

60 / 309 page

Am79C976

8/01/00

P R E L I M INARY

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Earlier members of the PCnet family of controllers had

to be re-initialized if the transmitter and/or the receiver

were not turned on during the original initialization, and

it was subsequently required to activate them, or if ei-

ther section was shut off due to the detection of a mem-

ory error, transmitter underflow, or transmit buffer error

condition. This restriction does not apply to the

Am79C976 device. The memory error and transmit

buffer error conditions cannot occur in the Am79C976

controller and the transmit underflow condition does

not stop the Am79C976 controller’s transmitter.

For compatibility with other PCnet family devices, re-

initialization may be done via the initialization block or

by setting the STOP bit in CSR0, followed by writing to

CSR15, and then setting the STRT bit in CSR0. Note

that this form of restart will not perform the same in the

Am79C976 controller as in the C-LANCE device. In

particular, setting the STRT bit causes the Am79C976

controller to reload the transmit and receive descriptor

pointers with their respective base addresses. This

means that the software must clear the descriptor

OWN bits and reset its descriptor ring pointers before

restarting the Am79C976 controller. The reload of de-

scriptor base addresses is performed in the C-LANCE

device only after initialization, so that a restart of the

C-LANCE without initialization leaves the C-LANCE

pointing at the same descriptor locations as before the

restart.

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Following reset, the transmitter and receiver of the

Am79C976 controller are disabled, so no descriptor or

data DMA activity will occur. The receiver will process

incoming frames to detect address matches, which are

counted in the RcvMissPkts register. No transmits will

occur except that pause frames may be sent (see flow

control section).

Setting the RUN bit in CMD0 (equivalent to setting

STRT in CSR0) causes the Am79C976 controller to

begin descriptor polling and normal transmit and re-

ceive activity. Clearing the RUN bit (equivalent to set-

ting STOP in CSR0) causes the Am79C976 controller

to halt all transmit, receive, and DMA transfer activities

abruptly.

The Am79C976 controller offers suspend modes that

allow stopping the device with orderly termination of all

network activity. Transmit and receive are controlled

separately.

Setting the RX_FAST_SPND bit in CMD0 suspends re-

ceiver activity after the current frame being received by

the MAC is complete. If no frame is being received

when RX_FAST_SPND is set, the receiver is sus-

pended immediately. After the receiver is suspended,

the RX_SUSPENDED bit in STAT0 is set and SPND-

INT interrupt bit in INT0 is set. Receive data and de-

scriptor DMA activity continues normally while the

receiver is fast suspended.

Setting the RX_SPND bit in CMD0 suspends the re-

ceiver in the same way as RX_FAST_SPND, but the

RX_SUSPENED bit and SPNDINT interrupt bit are

only set after any frames in the receive FIFO have been

completely transferred into system memory and the

corresponding descriptors updated. No receive data or

descriptor DMA activity will occur while the receiver is

suspended.

When the receiver is suspended, no frames will be re-

ceived into the receive FIFO, but frames will be

checked for address match and the RcvMissPkts

counter incremented appropriately, and frames will be

checked for Magic Packet match if Magic Packet mode

is enabled.

Setting the TX_FAST_SPND bit in CMD0 suspends

transmitter activity after the current frame being trans-

mitted by the MAC is complete. If no frame is being

transmitted when TX_FAST_SPND is set, the transmit-

ter is suspended immediately. After the transmitter is

suspended, the TX_SUSPENDED bit in STAT0 is set

and SPNDINT interrupt bit in INT0 is set. Transmit de-

scriptor and data DMA activity continues normally

while the transmitter is fast suspended.

Setting the TX_SPND bit in CMD0 suspends the trans-

mitter in the same way as TX_FAST_SPND, but the

TX_SUSPENDED bit and SPNDINT interrupt bit are

only set after any frames in the transmit FIFO have

been completely transmitted. No transmit descriptor or

data DMA activity will occur while the transmitter is sus-

pended.

When the transmitter is suspended, no frames will be

transmitted except for flow control frames (see Flow

Control section).

It is not meaningful to set both TX_SPND and

TX_FAST_SPND at the same time, nor is it meaningful

to set both RX_SPND and RX_FAST_SPND at the

same time. Doing so will cause unpredictable results.

However, transmit and receive are independent of each

other, so one may be suspended or fast suspended

while the other is running, suspended or fast sus-

pended.

For compatibility with other PCnet family devices, set-

ting the SPND bit in CSR5 with FASTSPNDE in CSR7

cleared is equivalent to setting both TX_SPND and

RX_SPND and clearing SPND with FASTSPNDE

cleared is equivalent to clearing both TX_SPND and

RX_SPND. Similarly, setting SPND with FASTSPNDE

set is equivalent to setting both TX_FAST_SPND and

R X _FAST _SPN D an d clear ing SPND w i th

FASTSPNDE set is equivalent to clearing both

TX_FAST_SPND and RX_FAST_SPND. While equiva-

lent, these methods are not identical, so software

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