AM79C976 datasheet(92/309 Pages) AMD

92 / 309 page

Am79C976

8/01/00

P R E L I M INARY

The contents of the SRAM_TYPE field are defined in

Table 15.

The width of the Flash memory (or EPROM) is 8 bits.

The memory can be as large as 16M X 8 bits.

The external memory bus uses the same address,

data, and control pins to access both Flash and

SSRAM memory, but it has separate chip select (or

chip enable) pins so that only one device can be se-

lected at a time. FLCS selects the Flash memory, while

ERCE selects the SSRAM. The Flash memory must

not be accessed when the Am79C976 controller is run-

ning (when the RUN bit in CMD0 is set to 1). Any ac-

cess to the Flash memory clears the RUN bit and

thereby abruptly stops all network and DMA opera-

tions.

ERA[19:0] provides 20 bits of address for the SSRAM

and the lower 20 bits of address for the Flash memory.

The higher 4 bits of address for the Flash memory are

shared with bits [11:8] of the SSRAM data bus

(ERD[11:8]). The lower 8 bits of the external memory

data bus ERD[7:0] are used by both the SSRAM and

the Flash. The high order 20 bits of the external mem-

ory data bus ERD[31:12] are used only by the SSRAM.

The output enable signal for the Flash (FLOE) shares a

pin with the SSRAM Address Advance signal (ERADV).

Figure 36 shows how the SSRAM and Flash can be

connected to the Am79C976 controller.

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The Am79C976 controller supports EPROM or Flash

as an Expansion ROM boot device. Both are config-

ured using the same methods and operate the same.

See Figure 3636. See the previous section on Expan-

sion ROM transfers for the PCI timing and functional

description of the transfer method.

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Table 15. SRAM_TYPE Field Encoding

SRAM_TYPE[1:0]

External Memory Type

Reserved

ZBT

Reserved

Pipelined Burst

ERCLK

EROE

A[19:0]

DQ[7:0]

L4 Controller

FLASH

A[23:20]

SSRAM

CLK

A[16:0]

CE1 OR CE2

D[31:0]

GW OR R/W

ADV

ADSP OR CEN

ERA[19:0]

ERD[31:0]

ERWE/FLWE

ERADV/FLOE

ERADSP/CEN

ERCE

FLCS

[11:8]

[7:0]

A17

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