AM79C976 datasheet(86/309 Pages) AMD

86 / 309 page

Am79C976

8/01/00

P R E L I M INARY

To control the auto-negotiation process, the Network

Port Manager generates MII Management Frames to

execute the procedure described below. (See Appen-

dix B, MII Management Registers, for the MII register

bit descriptions.)

The Network Port Manager is held in the IDLE state

while H_RESET is asserted, while the EEPROM is

being read and while the DISPM bit is set. When none

of these conditions are true, the Network Port Manager

proceeds through the following steps:

1. If XPHYRST is set, write to the PHY’s Control Reg-

ister (R0) to set the Soft Reset bit and cause the

PHY to reset. The Network Port Manager then peri-

odically reads the PHY’s Control Register (R0) until

the reset is complete.

2. If XPHYRST is not set or after the PHY reset is com-

plete, the PHY’s Status Register (R1) is read.

3. If the PHY’s Auto-Negotiation Ability bit (R1, bit 3) is

0 or if the XPHYANE bit in the Control2 Register is

0, write to the PHY’s Control Register (R0) to dis-

able auto-negotiation and set the speed and duplex

mode to the values specified by the XPHYSP and

XPHYFD bits in the Control2 Register “and”ed with

the appropriate bits from the PHY's Technology

Ability Field. Then proceed to step 8.

4. Otherwise write to the Auto-Negotiation Advertise-

ment Register (R4). Bits A0 to A5 of Technology

Ability field of R4 are taken from bits 15 to 11 in R1.

Bit A6 of the Technology Ability field indicates the

MAC's ability to respond to MAC Control Pause

frames. This bit is set equal to the value of the Ne-

gotiate Pause Ability (NPA) bit in the Flow Control

mote Fault bits are set to 0, and the Selector Field

is set to 00001 to indicate IEEE Std 802.3.

5. Write to the Control Register (R0) to restart Auto-

negotiation.

6. Poll R1 until the Auto-Negotiation Complete bit is

set to 1.

7. Read the Auto-Negotiation Link Partner Ability Reg-

ister (R5). Set the MAC's speed, duplex mode, and

pause ability to the highest priority mode that is

common to both PHY devices.

8. Poll R1 until the Link Status bit is 1. If Link Status is

not found to be 1 after two polls at 900 ms intervals,

go back to step 1.

9. Poll R1 at intervals of about 900 ms until the Link

Status bit is 0. Go to step 8.

When Auto-Negotiation is complete, the Network Port

Manager examines the MF Preamble Suppression bit

in PHY register 1. If this bit is set, the Network Port

Manager suppresses preambles on all frames that it

sends until one of the following events occurs:

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A complete bit description of the MII and Auto-

Negotiation registers can be found in Appendix B.

The Network Port Manager is not disabled when the

MDIO pin is held low when the MII Management Inter-

face is idle. If no PHY is connected, reads of the exter-

nal PHY's registers will result in read errors, causing

the MREINT interrupt to be asserted.

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The MII Management Interface (MDC and MDIO) can

be used to manage more than one external PHY de-

vice. The external PHY devices may or may not be con-

nected to the Am79C976 controller’s MII bus. For

example, two PHY devices can be connected to the

Am79C976 controller’s MII bus so that the MAC can

communicate over either a twisted-pair cable or a fiber-

optic link. Conversely, several Am79C976 controllers

may share a single integrated circuit that contains sev-

eral PHY devices with separate MII busses but with

only one MII Management bus. In this case, the MII

Management Interface of one Am79C976 controller

could be used to manage PHY devices connected to

different Am79C976 controllers.

If more than one PHY device is connected to the MII

bus, only one PHY device is allowed to be enabled at

any one time. Since the Network Port Manager can not

detect the presence of more than one PHY on the MII

bus, the host CPU is responsible for making sure that

only one PHY is enabled. The host CPU can use the

PHY Access Register to set the Isolate bit in the Con-

trol Register (Register 0, bit 10) of any PHY that needs

to be disabled.

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The Port Manager normally sets up the speed, duplex

mode, and flow control (pause) ability of the MAC

based on the results of auto-negotiation. However, it is

possible to operate the Am79C976 device with no MII

Management Interface connection, in which case the

Port Manager is not able to start the auto-negotiation

process or set up the MAC-based on auto-negotiation

results. This may happen if the Am79C976 controller is

connected to a multi-PHY device that has only one MII

Management Interface that is shared among several

PHYs.

If the Am79C976 controller is operating without a MII

Management Interface connection to its external PHY,

the host CPU can force the MAC into the desired state

by setting the DISPM bit in CMD3 Register to 1 to dis-

able the Port Manager, then writing to the following bits:

AM79C976 Datenblatt(PDF) 86 Page - Advanced Micro Devices

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