AM79C976 datasheet(96/309 Pages) AMD

96 / 309 page

Am79C976

8/01/00

P R E L I M INARY

tests on the external SRAM, internal SRAM access

logic, and the PC board interconnect.

The MBIST controller can determine the size of the ex-

ternal SRAM and verify its operation using the following

procedure:

1. Program SRAM_SIZE to the minimum allowed

value of 4.

2. Write DM_START and DM_FAIL_STOP (write

DATAMBIST bits 63:56 with 0x28). The remainder

of the DATAMBIST register ignores writes so it may

be written with arbitrary data or not written at all.

3. Read

DM_DONE

(DATAMBIST

bit

63)

and

DM_ERROR (DATAMBIST bit 62) until DM_DONE

is set.

4. If DM_ERROR is set, the memory is defective; re-

port the error and exit.

5. Program SRAM_SIZE to the maximum value of

0x8000 and repeat steps 2 and 3.

6. If DM_ERROR is zero, report the current value of

SRAM_SIZE as the SSRAM size.

7. If DM_ERROR is set, program SRAM_SIZE to one-

half the maximum (0x4000) and repeat steps 2

and 3.

8. Repeat, using the binary search algorithm, until the

SRAM size has been determined.

EEPROM Interface

The Am79C976 device includes an interface to an op-

tional 16-bit word-oriented 93Cxx-compatible serial

EEPROM that supports automatic address increment-

ing (sequential read). This EEPROM can be used for

storing initial values for Am79C976 registers. The con-

tents of this EEPROM are automatically loaded into the

selected registers after a reset operation or whenever

the host CPU requests an EEROM read operation.

Note that if the EEPROM is not included in the system,

the MAC address (and Magic Packet information, if

needed) must be initialized by the host CPU.

The Am79C976 device automatically detects the size

of the EEPROM. When the EEPROM decodes a read

command, it drives its DO pin low when the A0 address

bit is written to the DI pin. The Am79C976 device uses

this fact to detect the number of bits in the EEPROM

address and from this determines the EEPROM size.

Data in the EEPROM are interpreted as three-byte

entries that contain register address and register data

so that the system designer can choose which regis-

ters will automatically be loaded. In a typical system,

the EEPROM would be used to initialize the device’s

IEEE 802 physical address, the PCI Subsystem Vendor

ID, LED configuration, SSRAM configuration, and other

hardware configuration information. For compatibility

with older PCnet family software the Address PROM

Space should be loaded from the EEPROM. See the

Address PROM Space section for details.

Only the memory-mapped registers can be loaded

from the EEPROM. While the CSRs and BCRs are not

memory-mapped, all useful bits in the CSRs and BCRs

are aliased into memory-mapped registers so that all

useful bits can be loaded from the EEPROM.

Most of the memory-mapped registers are 32 bits wide

and occupy 4 bytes of memory space each. For exam-

ple, the CMD2 Register is located at offset 50h from the

memory base address. Its least significant 16 bits can

be accessed at offset 50h, and its most significant 16

bits can be accessed at offset 52h. Register data are

loaded from the EEPROM 16 bits at a time, so that the

high order bits of a register are loaded independently

from the low order bits.

The EEPROM Access Register gives the host CPU di-

rect access to the interface pins so that it can read from

or write to the EEPROM.

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After the trailing edge of the RESET signal or after the

PREAD bit in BCR19 is set, the Am79C976 device be-

gins to read data from the EEPROM. Data from the EE-

PROM are interpreted as a string of 3-byte entries.

Each entry contains a 1-byte register address and a

2-byte register data field. The register address field

contains the offset of the target register divided by 2.

The initialization logic writes the contents of the register

data field into the register selected by the register ad-

dress byte.

Since EEPROM data are loaded two bytes at a time,

the least significant bit of the target register offset is

omitted from the address field. Only bits 8:1 are in-

cluded. Therefore, the register address byte contains

the offset of the target register divided by two. For ex-

ample, the Control2 Register (CTRL2) is a 32-bit regis-

ter located at offset 70h (relative to the contents of the

Memory-Mapped I/O Base Address Register). There-

fore, the byte stream 38h, 02h, 05h would cause the

value 0205h to be loaded into bits [15:0] of CTRL2, and

39h, 00h, 03h would cause the value 0003h to be

loaded into bits [31:16] of the same register.

If the value of the address byte is 0FFh, the following

2-byte field is interpreted as a 16-bit CRC code rather

than as register data. The CRC code covers all

EEPROM data up to and including the address byte of

the entry containing the CRC. All EEPROM data after

the CRC code word are ignored.

The CRC code used is CRC-16, which is based on the

generator polynomial x16 + x15 + x2 + 1.

The EEPROM must contain data for an odd number of

registers so that the CRC is aligned on a 16-bit word

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