AS8515 datasheet(12/65 Pages) AMSCO

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AS8515

Datasheet - AS8515 To p Die Overview

7.5 VSUP Under-voltage Reset

When VSUP drops below VSUVR_ON, the RESET_VSUP_N switches back to low level. This is treated as a master reset and will have the

highest priority over all other signals. In this case, the regulators, LIN transceiver, and all other blocks are shut off, and the device comes to a

complete stop. The device returns to the normal mode when VSUP rises over VSUVR_OFF again irrespective of the mode it was in prior to this

under-voltage condition.

7.6 Reset

RESET module generates an active-low reset signal for the external circuitry supplied by VCC. The behavior of the reset output is depicted in

Figure 4 in different cases. As shown, RESET signal is affected by an under-voltage condition on VCC and Watchdogs which are described in

detail in the subsequent sections.

The reset period can be one-time programmed to 4, 16 and 32 ms with a default value of 8 ms.

Figure 4. Reset Functionality

7.7 VCC Under-voltage Reset

When VCC drops below VUVR_ON, the RESET_VCC_N switches back to low level. This event generates a reset output. The reset output is

released again only a reset period (tRes) later after VCC rises above VUVR_OFF. If the time difference between the VCC falling below VUVR_ON

and rising above VUVR_OFF is less than trr, there will be no reset output. The reset output is affected in the conditions like over-temperature

shutdown and temporary shutdown only through VCC under voltage.

VCC

VSUP

VUVR_OFF

tRes

trr

T>Tj

T<Tj

t<trr

tRes

RESET

Start-up

Over-temp

Shutdown

Glitch in

VSUP

VSUP UV

SC Current

Limitation Active

VUVR_ON

tRes

Reset by

Watchdog

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