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AS8515 Datenblatt(PDF) 26 Page - ams AG |
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AS8515 Datenblatt(HTML) 26 Page - ams AG |
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26 / 65 page ![]() www.ams.com Revision 0.7 26 - 65 AS8515 Datasheet - AS8515 To p Die Overview 7.17.1 Tx Timeout Watchdog 7.17.2 Temperature Limiter 7.18 Top Die Registers The serial interface can be used for communication between AS8515 and an external microcontroller. The device is only a slave and the microcontroller has to initiate the communication. The device can be configured by writing into the control registers and the diagnostic information can be read out from the diagnostic registers. Pin CST is used as chip select for SPI communication. A total of 32 registers, each of 8-bits which include configuration, diagnostic, and backup are available. The registers can be accessed using the 4-wire serial interface. Table 28 provides a description of all AS8515 Top die registers. Table 26. Tx Timeout Watchdog Symbol Parameter Conditions Min Typ Max Units tlin_wdog Timeout period for the dominant state 0.5 1 2 s Table 27. Temperature Limiter Symbol Parameter Conditions Min Typ Max Units Tsd Shut down temperature Junction temperature 155 170 185 ºC Totset Over-temperature warning 142 157 172 ºC Tret Return temperature 125 140 155 ºC Table 28. AS8515 Top Die Registers Address Register Name Default Value R/W Description Configuration and Control Registers 0x00 Reserved 0x01 Reserved 0x02 Reserved 0x03 Device Configuration Register On POR_VCC 0000_1100 R/W D0 Reserved D1 Voltage Attenuator Enable Bit. 0 Disabled, 1 Enabled D2 Enable/Disable Over Temperature Monitor 0 Disabled, 1 Enabled D3 Enable/Disable LIN Transceiver 0 Disabled, 1 Enabled D4 Reserved D5-D7 Reserved 0x04 Device Control Register On POR_VSUP 0000_0001 R/W D0 High-slew / Low-slew control 1 High-slew, 0 Low-slew D1-D7 Reserved 0x05 Temporary Shutdown Register On POR_VCC 0000_0000 R/W D0 Temporary shutdown control bit 1 Enter temporary shutdown D1-D7 Reserved 0x06 Window Watch Dog Trigger Register On POR_VCC 0000_0000 W D0 Window Watchdog trigger bit D1 Timeout Watchdog trigger bit Upon a trigger, the bit will be cleared within 2 internal clock cycles. D2-D7 Reserved 0x07 Reserved 0x0A Reserved 0x0B Reserved |
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