AS8515 datasheet(34/65 Pages) AMSCO

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AS8515

Datasheet - AS8515 Bottom Die Overvi ew

TDATA_STATUS_RD is the time period during which the micro-controller should complete reading of data and status from the device. If reading is

carried out beyond this time period, then, ADC performance will degrade for next sample generation. Status register gets cleared automatically

only when micro-controller reads this register. Data in the channel registers is changed after TDATA_VALID duration. Ensure that data channel

registers and status registers are not read during the TDATA_INVALID duration.

Example:

Configuration registers are set as follows:

CLK_REG = 8’b0010_0000

DEC_REG_R1_I = 0100_0101

DEC_REG_R2_I = 1100_0101

FIR_CTL_REG_I = 0000_0100

ADC is configured to a data rate of 1KHz, CHOP_CLK to 2KHz, and Modulator clock to 1MHz, Decimation ratio of CIC1 = 64, and Decimation

ratio of CIC2 = 4. With these settings the various time periods as shown in the Figure 23 are as follows:

TDATA_STATUS_RD = 100

μsec

(TDATA_STATUS_RD = (1/mod_clk) * R1 * [((mod_clk/(2*chop_clk))*(1/R1)) - 2.5)

TDATA_INVALID = 8

μsec

TADC = 1msec

TDATA_VALID = TADC - TDATA_INVALID = 1msec - 8

μsec

CHOP_CLK and POR_N are internal signals of the device.

Table 29 provides valid combinations of Modulator clock, Chopper clock and Decimation R1 and the corresponding values of TDATA_STATUS_RD and

TADC.

8.8.1 Soft-reset of Device Using Bit D[7] of Reset Register 0x09

It is possible to soft-reset the device by writing “0” into D[7] bit of Reset Register at 0x09. On applying soft-reset, the device enters into

initialization state and D[6] bit changes back to “1”. The duration period of Initialization is 500

μsec, and, during this period, INT pin toggles at the

rate of internal low power oscillator. Toggling on INT during the period of initialization should be ignored in the system. Device configuration and

activation should be carried out only after the initialization period. See Figure 24 for the timing details of the sequence of device initialization on

soft-reset.

Table 29. Valid Combinations of Modulator Clock, Chopper Clock and Decimation Ratio R1

Modulator Clock

Chopper Frequency

CHOP_CLK

Decimation Ratio R1

TDATA_STATUS_RD

TADC

R2/(2*CHOP_CLK)

for R2=4

1.024MHz

2KHz

1usec * 64 * [4 - 2.5] = 96usec

1mSec

2.048MHz

2KHz

0.5usec * 64 * [8 - 2.5] = 176usec

1mSec

2.048MHz

2KHz

128

0.5usec * 128 * [4 - 2.5] = 96usec

1mSec

2.048MHz

4KHz

0.5usec * 64 * [4 - 2.5] = 48usec

0.5mSec

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