AS8515 datasheet(31/65 Pages) AMSCO

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AS8515

Datasheet - AS8515 Bottom Die Overvi ew

Figure Notes:

1. Device soft reset can be written in any of the following states STOP, A_STB, SBM_ON, SBM_OFF by writing “0” into D[7] of the RESET

_REG (Address 0X09).

2. Measurement path of soft reset should be written in any the states, STOP, SBM_OFF by writing “0” into D[6] of the RESET _REG (Address

0X09).

3. When soft reset is used for the measurement path or for the device, external clock needs to be disabled if the system clock is external

clock in the application.

8.7.1 Normal Mode 1 (NOM1)

On Power-on-reset of the device, AS8515 goes into STOP State.

Transition to Normal mode1 (NOM1) occurs when the “START BIT” D0 of Mode Control Register MOD_CTL_REG in Table 49 is set to “1”

through the serial port SPI. Data Rate of voltage and current channels can be independently programmed and both the channels generate

interrupts for every output available from ADC. The interrupt signal is generated on the INT pin. The width of the interrupt pulse is eight cycles of

lp_clk. The data is stable up to the next interrupt. If the data rate is different for the two channels, the interrupt rate would follow the higher rate

among the two channels. Data update can be known by reading the status register. The functionality is explained in the waveform shown in

Figure 19. When the device is configured to NORMAL Mode1 from any mode the configuration should be through the STOP state only.

Figure 19. Normal Mode 1

8.7.2 Normal Mode 2 (NOM2)

NOM2 differs from NOM1 in such a way that it allows for a relaxed data rate at a period of TMC by programming the corresponding register as

long as the amplitude of current is less than a programmed threshold ITHC. However, when, the measured input signal exceeds the programmed

threshold, the data rate is changed to the rate of NOM1 mode.

Transition to NOM2 occurs when the “START BIT” D0 of Mode Control register MOD_CTL_REG in Table 49 is set to 1 and mode control bits to

01 through SPI. In this mode the data rate should be programmed with the time of TMC. An interrupt signal is generated on INT at the rate of TMC

secs with a pulse width of eight cycles of lp_clk. The data is stable up to the next interrupt. The data sample is compared against the programmed

threshold and when it is exceeded, the data sampling rate is changed to provide data at the data rate of NOM1 mode. However, as soon as the

data sample amplitude falls below the programmed threshold, the sampling rate is restored to provide data at the rate of TMC. The functionality is

illustrated in the waveform Figure 20.

Sampling with f1

INT at f1 rate from

current channel

Current Channel

DATA Register

START

STOP

V,T

Sampling with f2

Voltage Channel

DATA Register

Interrupt fromthe current channel is at f1 rate which is integer multiple of f2 rate fromvoltage channel

IDATA

V,TDATA

TINT

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