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MPC5644BCAMMJ1 Datenblatt(PDF) 81 Page - NXP Semiconductors |
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MPC5644BCAMMJ1 Datenblatt(HTML) 81 Page - NXP Semiconductors |
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81 / 116 page ![]() Electrical Characteristics MPC5646C Microcontroller DataSheet, Rev. 7 NXP Semiconductors 81 IINJ SR — Input current Injection Current injection on one ADC_1 input, different from the converted one VDD = 3.3 V ± 10% −5 — 5 mA VDD = 5.0 V ± 10% −5 — 5 INLP CC T Absolute Integral non-linearity-Preci se channels No overload 1 3 LSB INLS CC T Absolute Integral non-linearity- Standard channels No overload 1.5 5 LSB DNL CC T Absolute Differential non-linearity No overload 0.5 1 LSB OFS CC T Absolute Offset error —2 LSB GNE CC T Absolute Gain error —2 LSB TUEP9 CC P Total Unadjusted Error for precise channels, input only pins T Without current injection −6 6 LSB T With current injection −8 8 LSB TUES(9) CC T Total Unadjusted Error for standard channel P Without current injection −10 10 LSB T With current injection −12 12 LSB 1 V DD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified. 2 Analog and digital V SS_HV must be common (to be tied together externally). 3 PA3, PA7, PA10, PA11 and PE12 ADC_1 channels are coming from V DD_HV_B domain hence VDD_HV_ADC1 should be within ±100 mV of VDD_HV_B when these channels are used for ADC_1. 4 VDD_HV_ADC1 can operate at 5V condition while V DD_HV_B can operate at 3.3V provided that ADC_1 channels coming from VDD_HV_B domain are limited in max swing as VDD_HV_B. 5 V AINx may exceed VSS_ADC1 and VDD_ADC1 limits, remaining on absolute maximum ratings, but the results of the conversion will be clamped respectively to 0x000 or 0xFFF. 6 During the sample time the input capacitance C S can be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach its final voltage level within tADC1_S. After the end of the sample time tADC1_S, changes of the analog input voltage have no effect on the conversion result. Values for the sample clock tADC1_S depend on programming. 7 Conversion time = Bit evaluation time + Sampling time + 1 Clock cycle delay. 8 Refer to ADC conversion table for detailed calculations. Table 43. Conversion characteristics (12-bit ADC_1) (continued) Symbol C Parameter Conditions1 Value Unit Min Typ Max |
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