MPC5644BCAMMJ1 datasheet(82/116 Pages) NXP

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MPC5646C Microcontroller DataSheet, Rev. 7

Electrical Characteristics

NXP Semiconductors

4.18

Fast Ethernet Controller

MII signals use CMOS signal levels compatible with devices operating at 3.3 V. Signals are not TTL compatible. They follow

the CMOS electrical characteristics.

4.18.1

MII Receive Signal Timing (RXD[3:0], RX_DV, RX_ER, and RX_CLK)

The receiver functions correctly up to a RX_CLK maximum frequency of 25 MHz +1%. There is no minimum frequency

requirement. In addition, the system clock frequency must exceed four times the RX_CLK frequency in 2:1 mode and two times

the RX_CLK frequency in 1:1 mode.

Figure 21. MII receive signal timing diagram

4.18.2

MII Transmit Signal Timing (TXD[3:0], TX_EN, TX_ER, TX_CLK)

The transmitter functions correctly up to a TX_CLK maximum frequency of 25 MHz +1%. There is no minimum frequency

requirement. In addition, the system clock frequency must exceed four times the TX_CLK frequency in 2:1 mode and two times

the TX_CLK frequency in 1:1 mode.

The transmit outputs (TXD[3:0], TX_EN, TX_ER) can be programmed to transition from either the rising or falling edge of

TX_CLK, and the timing is the same in either case. This options allows the use of non-compliant MII PHYs.

Refer to the Fast Ethernet Controller (FEC) chapter of the MPC5646C Reference Manual for details of this option and how to

enable it.

9 Total Unadjusted Error: The maximum error that occurs without adjusting Offset and Gain errors. This error is a

combination of Offset, Gain and Integral Linearity errors.

Table 44. MII Receive Signal Timing

Spec

Characteristic

Min

Max

Unit

RXD[3:0], RX_DV,

RX_ER to RX_CLK

setup

5—

RX_CLK to

RXD[3:0], RX_DV,

RX_ER hold

5—

RX_CLK pulse width

high

35%

65%

RX_CLK period

RX_CLK pulse width

low

35%

65%

RX_CLK period

RX_CLK (input)

RXD[3:0] (inputs)

RX_DV

RX_ER

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