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STM32U595AI Datenblatt(PDF) 314 Page - STMicroelectronics

Teilenummer STM32U595AI
Bauteilbeschribung  Ultra-low-power Arm® Cortex®-M33 32-bit MCUTrustZone®FPU,240 DMIPS, up to 4 MB Flash, 2.5 MB SRAM, LTDC, MIPI® DSI
PDF  377 Pages
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Hersteller  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
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STM32U595AI Datenblatt(HTML) 314 Page - STMicroelectronics

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Electrical characteristics
STM32U59xxx
314/377
DS13633 Rev 1
Figure 58. Asynchronous multiplexed PSRAM/NOR write waveforms
NBL
Data
FMC_ NEx
FMC_ NBL[1:0]
FMC_ AD[15:0]
tv(BL_NE)
th(Data_NWE)
FMC_NOE
Address
FMC_ A[25:16]
tv(A_NE)
tw(NWE)
FMC_NWE
tv(NWE_NE)
t h(NE_NWE)
th(A_NWE)
th(BL_NWE)
t v(A_NE)
tw(NE)
MS32756V1
Address
FMC_NADV
t v(NADV_NE)
tw(NADV)
tv(Data_NADV)
th(AD_NADV)
FMC_NWAIT
tsu(NWAIT_NE)
th(NE_NWAIT)
Table 129. Asynchronous multiplexed PSRAM/NOR write timings(1)
Symbol
Parameter
Min
Max
Unit
tw(NE)
FMC_NE low time
3 × tHCLK - 1
3 × tHCLK
ns
tv(NWE_NE)
FMC_NEx low to FMC_NWE low
tHCLK - 1
tHCLK
tw(NWE)
FMC_NWE low time
2 × tHCLK - 0.5 2 × tHCLK + 1
th(NE_NWE)
FMC_NWE high to FMC_NE high hold time
tHCLK
-
tv(A_NE)
FMC_NEx low to FMC_A valid
-
1
tv(NADV_NE)
FMC_NEx low to FMC_NADV low
0
2
tw(NADV)
FMC_NADV low time
tHCLK - 0.5
tHCLK + 1
th(AD_NADV)
FMC_AD(adress) valid hold time after FMC_NADV high)
tHCLK - 4.5
-
th(A_NWE)
Address hold time after FMC_NWE high
tHCLK - 0.5
-
th(BL_NWE)
FMC_BL hold time after FMC_NWE high
tHCLK - 0.5
-
tv(BL_NE)
FMC_NEx low to FMC_BL valid
-
0.5
tv(Data_NADV)
FMC_NADV high to Data valid
-
tHCLK + 2
th(Data_NWE)
Data hold time after FMC_NWE high
tHCLK
-
1. Evaluated by characterization. Not tested in production.



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