STM32U595AI datasheet(319/377 Pages) STMICROELECTRONICS

319 / 377 page

DS13633 Rev 1

319/377

STM32U59xxx

Electrical characteristics

343

Figure 61. Synchronous non-multiplexed NOR/PSRAM read timings

FMC_CLK

FMC_NEx

FMC_A[25:0]

FMC_NOE

FMC_D[15:0]

FMC_NWAIT

(WAITCFG = 1b,

WAITPOL + 0b)

FMC_NWAIT

(WAITCFG = 0b,

WAITPOL + 0b)

tw(CLK)

Data latency = 0

td(CLKL-NExL)

td(CLKH-NExH)

td(CLKL-AV)

td(CLKH-AIV)

td(CLKL-NOEL)

td(CLKH-NOEH)

tsu(DV-CLKH)

th(CLKH-DV)

tsu(DV-CLKH)

th(CLKH-DV)

tsu(NWAITV-CLKH)

th(CLKH-NWAITV)

tsu(NWAITV-CLKH)

t h(CLKH-NWAITV)

tsu(NWAITV-CLKH)

th(CLKH-NWAITV)

MS32759V1

FMC_NADV

td(CLKL-NADVL)

td(CLKL-NADVH)

Table 133. Synchronous non-multiplexed NOR/PSRAM read timings(1)

Symbol

Parameter

Min

Max

Unit

tw(CLK)

FMC_CLK period

2 × tHCLK - 0.5

td(CLKL-NExL)

FMC_CLK low to FMC_NEx low (x=0..2)

td(CLKH-NExH)

FMC_CLK high to FMC_NEx high (x= 0…2)

tHCLK - 0.5

td(CLKL-NADVL)

FMC_CLK low to FMC_NADV low

2.5

td(CLKL-NADVH)

FMC_CLK low to FMC_NADV high

td(CLKL-AV)

FMC_CLK low to FMC_Ax valid (x=0…25)

2.5

td(CLKH-AIV)

FMC_CLK high to FMC_Ax invalid (x=0…25)

tHCLK - 0.5

td(CLKL-NOEL)

FMC_CLK low to FMC_NOE low

1.5

td(CLKH-NOEH)

FMC_CLK high to FMC_NOE high

tHCLK + 1

tsu(DV-CLKH)

FMC_D[15:0] valid data before FMC_CLK high

th(CLKH-DV)

FMC_D[15:0] valid data after FMC_CLK high

tsu(NWAIT-CLKH)

FMC_NWAIT valid before FMC_CLK high

th(CLKH-NWAIT)

FMC_NWAIT valid after FMC_CLK high

2.5

1. Evaluated by characterization. Not tested in production.

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