STM32U595AI datasheet(326/377 Pages) STMICROELECTRONICS

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Electrical characteristics

STM32U59xxx

326/377

DS13633 Rev 1

tw(CLKH) OCTOSPI clock

high and low time

(odd division)

PRESCALER[7:0] = n

(n = 2, 4, 6,..254)

(n/2) × t(CLK)

/(n+1) - 0.5

(n/2) × t(CLK)

/(n+1) + 0.5

tw(CLKL)

((n/2)+1) × t(CLK)

/(n+1) - 0.5

((n/2)+1) × t(CLK)

/(n+1) + 0.5

tv(CLK)

Clock valid time

t(CLK) + 2

th(CLK)

Clock hold time

t(CLK)/2 - 0.5

VODr(CLK)

(5)

CLK, NCLK

crossing level on

CLK rising edge

VDD = 1.8 V

925

1040

VODf(CLK)

(5)

CLK, NCLK

crossing level on

CLK falling edge

VDD = 1.8 V

870

1105

tw(CS)

Chip select high

time

-3 × t(CLK)

tv(DQ)

Data input valid

time

-0

tv(DS)

Data strobe input

valid time

th(DS)

Data strobe input

hold time

-0

tv(RWDS)

Data strobe output

valid time

3 × t(CLK)

tsr(DQ)

tsf(DQ)

Data input setup

time

Voltage range 1

-0.25

t(CLK)/2 - 1.25(6)

Voltage range 4

t(CLK)/2 - 1.75(6)

thr(DQ)

thf(DQ)

Data input hold

time

Voltage range 1

1.25

Voltage range 4

1.75

tvr(OUT)

tvf(OUT)

Data output valid

time DHQC = 0

Voltage range 1

9.5

Voltage range 4

19.5

Data output valid

time DHQC = 1

Voltage range 1

All prescaler values

(except 0)

-t(CLK)/4 + 0.5

t(CLK)/4 + 1.25

thr(OUT)

thf(OUT)

Data output hold

time DHQC = 0

Voltage range 1

Voltage range 4

7.75

thr(OUT)

Data output hold

time DHQC = 1

Voltage range 1

All prescaler values

(except 0)

t(CLK)/4 - 0.5

1. Evaluated by characterization. Not tested in production.

2. Delay block activated.

3. Maximum frequency values are given for a RWDS to DQ skew of maximum ±1.0 ns.

4. Activating DHQC is mandatory to reach this frequency.

5. Crossing results are in line with specification, except for PA3/PB5 CLK that exceed slightly the specification.

Table 139. OCTOSPI characteristics in DTR mode (with DQS)/HyperBus(1)(2) (continued)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

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