ATtiny45 datasheet(70/196 Pages) ATMEL

70 / 196 page

7598H–AVR–07/09

ATtiny25/45/85

The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOTTOM. The

Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM

value.

In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the

OC0x pins. Setting the COM0x1:0 bits to two will produce a non-inverted PWM. An inverted

PWM output can be generated by setting the COM0x1:0 to three: Setting the COM0A0 bits to

one allows the OC0A pin to toggle on Compare Matches if the WGM02 bit is set. This option is

not available for the OC0B pin (See Table 12-3 on page 73). The actual OC0x value will only be

visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is

generated by clearing (or setting) the OC0x Register at the Compare Match between OCR0x

and TCNT0 when the counter increments, and setting (or clearing) the OC0x Register at Com-

pare Match between OCR0x and TCNT0 when the counter decrements. The PWM frequency for

the output when using phase correct PWM can be calculated by the following equation:

The N variable represents the prescale factor (1, 8, 64, 256, or 1024).

The extreme values for the OCR0A Register represent special cases when generating a PWM

waveform output in the phase correct PWM mode. If the OCR0A is set equal to BOTTOM, the

output will be continuously low and if set equal to MAX the output will be continuously high for

non-inverted PWM mode. For inverted PWM the output will have the opposite logic values.

At the very start of period 2 in Figure 12-7 OCn has a transition from high to low even though

there is no Compare Match. The point of this transition is to guaratee symmetry around BOT-

TOM. There are two cases that give a transition without Compare Match.

• OCR0A changes its value from MAX, like in Figure 12-7. When the OCR0A value is MAX the

OCn pin value is the same as the result of a down-counting Compare Match. To ensure

symmetry around BOTTOM the OCn value at MAX must correspond to the result of an

up-counting Compare Match.

• The timer starts counting from a value higher than the one in OCR0A, and for that reason

misses the Compare Match and hence the OCn change that would have happened on the

way up.

12.7

Timer/Counter Timing Diagrams

The Timer/Counter is a synchronous design and the timer clock (clk

T0) is therefore shown as a

clock enable signal in the following figures. The figures include information on when Interrupt

Flags are set. Figure 12-8 contains timing data for basic Timer/Counter operation. The figure

shows the count sequence close to the MAX value in all modes other than phase correct PWM

mode.

fOCnxPCPWM

clk_I/O

510

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