ATtiny45 datasheet(22/196 Pages) ATMEL

22 / 196 page

7598H–AVR–07/09

ATtiny25/45/85

6.1.1

CPU Clock – clk

CPU

The CPU clock is routed to parts of the system concerned with operation of the AVR core.

Examples of such modules are the General Purpose Register File, the Status Register and the

Data memory holding the Stack Pointer. Halting the CPU clock inhibits the core from performing

general operations and calculations.

6.1.2

I/O Clock – clk

I/O

The I/O clock is used by the majority of the I/O modules, like Timer/Counter. The I/O clock is

also used by the External Interrupt module, but note that some external interrupts are detected

by asynchronous logic, allowing such interrupts to be detected even if the I/O clock is halted.

6.1.3

Flash Clock – clk

FLASH

The Flash clock controls operation of the Flash interface. The Flash clock is usually active simul-

taneously with the CPU clock.

6.1.4

ADC Clock – clk

ADC

The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks

in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion

results.

6.1.5

Internal PLL for Fast Peripheral Clock Generation - clk

PCK

The internal PLL in ATtiny25/45/85 generates a clock frequency that is 8x multiplied from a

source input. The source of the PLL input clock is the output of the internal RC oscillator having

a frequency of 8.0 MHz. Thus the output of the PLL, the fast peripheral clock is 64 MHz. The fast

peripheral clock, or a clock prescaled from that, can be selected as the clock source for

Timer/Counter1. See the Figure 6-2 on page 23.

The PLL is locked on the RC oscillator and adjusting the RC oscillator via OSCCAL register will

adjust the fast peripheral clock at the same time. However, even if the RC oscillator is taken to a

higher frequency than 8 MHz, the fast peripheral clock frequency saturates at 85 MHz (worst

case) and remains oscillating at the maximum frequency. It should be noted that the PLL in this

case is not locked any longer with the RC oscillator clock.

Therefore, it is recommended not to take the OSCCAL adjustments to a higher frequency than 8

MHz in order to keep the PLL in the correct operating range. The internal PLL is enabled only

when the PLLE bit in PLLCSR is set or the PLLCK fuse is programmed (‘0’). The bit PLOCK

from PLLCSR is set when PLL is locked.

Both internal RC oscillator and PLL are switched off in power down and stand-by sleep modes.

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